Teridian 71M6403, Manual

Page: 48 / 75

71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 48 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
Fault, Reset, Power-Up
Reset Mode: When the RESETZ pin is pulled low, all digital activity in the chip stops while analog circuits are still active.
Additionally, all I/O RAM bits are cleared..
When RESETZ goes high the MPU will begin executing its preboot and boot sequences from address 00. See the security
section for more description of preboot and boot.
Chopping Circuitry
As explained in the hardware section, the bits of the I/O RAM register CHOP_ENA[1:0] have to be toggled in between
multiplexer cycles to achieve the desired elimination of DC offset.
The amplifier within the reference is auto-zeroed by means of an internal signal that is controlled by the CHOP_EN bits. When
this signal is HIGH, the connection of the amplifier inputs is reversed. This preserves the overall polarity of the amplifier gain but
inverts the input offset. By alternately reversing the connection, the offset of the amplifier is averaged to zero. The function of the
two bits of the
CHOP_EN register are described in Table 59.
CHOP_EN[1] CHOP_EN[0] Function
0 0 Toggle chop signal
0 1 Reference connection positive
1 0 Reference connection reversed
1 1 Toggle chop signal
Table 59: CHOP_EN Bits
For automatic chopping, the CHOP_EN bits are set to either 00 or 11. In this mode, the polarity of the signals feeding the
reference amplifier will be automatically toggled for each multiplexer cycle as shown in Figure 16. With an even number of
multiplexer cycles in each accumulation interval, the number of cycles with positive reference connection will equal the number
of cycles with reversed connection, and the offset for each sampled signal will be averaged to zero. This sequence is acceptable
when only the primary signals (circuit breaker voltage, circuit breaker current) are of interest.
Accumulation Interval m
MUX
cycle n
MUX
cycle 2
MUX
cycle 3
Chop Polarity
Positive Positive
Positive Positive
Re-
versed
Re-
versed
Re-
versed
Re-
versed
MUX
cycle n
MUX
cycle 1
MUX
cycle 1
MUX
cycle 1
Accumulation Interval m+1
CE_BUSY interrupt
(falling edge)
XFER_BUSY interrupt
(falling edge)
Accumulation Interval m+2
Positive
Positive
Re-
versed
Figure 16: Chop Polarity w/ Automatic Chopping
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