71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 49 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
Program Security
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations are blocked.
This guarantees the security of the user’s MPU and CE program code. Security is enabled by MPU code that is executed in a 32
cycle preboot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to perform
a global erase of the flash memory, followed by a chip reset. Global flash erase also clears the CE PRAM.
The first 32 cycles of the MPU boot code are called the preboot phase because during this phase the ICE is inhibited. A read-
only status bit,
PREBOOT
(SFR 0xB2[7]), identifies these cycles to the MPU. Upon completion of the preboot sequence, the ICE
can be enabled and is permitted to take control of the MPU.
SECURE
(SFR 0xB2[6]), the security enable bit, is reset whenever the MPU is reset. Hardware associated with the bit permits
only ones to be written to it. Thus, preboot code may set
SECURE
to enable the security feature but may not reset it. Once
SECURE
is set, the preboot code is protected and no external read of program code is possible.
Specifically, when
SECURE
is set:
•
The ICE is limited to bulk flash erase only.
•
Page zero of flash memory, the preferred location for the user’s preboot code, may not be page-erased by either MPU or
ICE. Page zero may only be erased with global flash erase. Note that global flash erase erases CE program RAM whether
SECURE
is set or not.
•
Writes to page zero, whether by MPU or ICE, are inhibited.
Additionally, by setting the I/O RAM register
ECK_DIS
to 1, the emulator clock is disabled, inhibiting access to the program with
the emulator.
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