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71M6403

Electronic Trip Unit

SEPTEMBER 2006

Page: 64 of 75

©

2006 TERIDIAN Semiconductor Corporation

REV 1.0

SPECIFICATIONS

Electrical Specifications

ABSOLUTE MAXIMUM RATINGS

Supplies and Ground Pins:

V3P3D, V3P3A

−

0.5V to 4.6V

| V3P3D - V3P3A |

0V to 0.5V

VLCD

-0.5V to 7V

GNDD

-0.5V to +0.5V

Analog Output Pins:

VREF, VBIAS

-1mA to 1mA,
-0.5 to V3P3A+0.5V

V2P5

-1mA to 1mA,
-0.5V to 3.0V

Analog Input Pins:

I0, I1, I2, I3, I4, I5, V2, INEUTRAL

-0.5V to V3P3A+0.5V

CK38

-0.5V to 3.0V

RX

-0.5V to 3.6V

OPT_RX

-1mA to 1mA
-0.5 to V3P3A+0.5V

Digital Input Pins:

DIO0-21, E_RXTX, E_RST, E_ISYNC/BRKRQ

-0.5 to 6V

RESETZ

-0.5 to V3P3D+0.5V

All Other Pins:

Input pins

-5mA to 5mA
-0.5V to V3P3D+0.5V

Output pins

-30mA to 30mA
-0.5 to V3P3D+0.5V

Temperature:

Operating junction temperature (peak, 100ms)

140 °C

Operating junction temperature (continuous)

125 °C

Storage temperature

−

45 °C to 165 °C

Solder temperature – 10 second duration

250 °C

ESD Stress:

Pins I0, I1, I2, I3, I4, I5, RX, TX, E_RST, E_TCLK, E_RXTX, E_TBUS[n]

4kV

All other pins

2kV

Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA.

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Summary of Contents for 71M6403

Page 1: ...tor ICE and development tools a powerful real time signal monitoring tool programming libraries and reference designs enable rapid development of advanced switchgear MPU TIMERS I0 I1 I2 I3 CK38 CK VRE...

Page 2: ...utation Engine CE 11 CE Functional Overview 12 Real Time Monitor 13 Power Up Short Circuit Detection Time 13 80515 MPU Core 14 80515 Overview 14 Memory Organization 14 Special Function Registers SFRs...

Page 3: ...ers 41 I 2 C Interface EEPROM 41 Test Ports 42 FUNCTIONAL DESCRIPTION 44 System Timing Summary 44 Data Flow 46 CE MPU Communication 46 Fault Reset Power Up 48 Chopping Circuitry 48 Program Security 49...

Page 4: ...RECOMMENDED OPERATING CONDITIONS 65 LOGIC LEVELS 65 SUPPLY CURRENT 66 2 5V VOLTAGE REGULATOR 66 VREF VBIAS 67 ADC CONVERTER VDD REFERENCED 68 OPTICAL INTERFACE 68 TEMPERATURE SENSOR 68 LCD BOOST 69 LC...

Page 5: ...Sequence 47 Figure 16 Chop Polarity w Automatic Chopping 48 Tables Table 1 Inputs Selected in Regular and Alternate Multiplexer Cycles EQU 5 8 Table 2 CE DRAM Locations for ADC Results 12 Table 3 Str...

Page 6: ...able 39 The TCON Register 31 Table 40 The TCON Bit Functions 31 Table 41 The IRCON Register 31 Table 42 The IRCON Bit Functions 31 Table 43 External MPU Interrupts 32 Table 44 Control Bits for Externa...

Page 7: ...TZ WAKE VBIAS DMUX TMUX CONFIGURATION PARAMETERS VDRV GNDA I4 TEMP September 9 2006 CK_GEN CK32 CK_EN CLK divider VOLTAGE BOOST LCD_BSTEN LCD_IBST VREF VREF_DIS MUX CTRL MUX_DIV CHOP_EN STRT I5 MUX CK...

Page 8: ...he chip is shown in Figure 1 A detailed description of various hardware blocks follows External Components The 71M6403 is optimized for fast startup To achieve this an external 19 6608 MHz oscillator...

Page 9: ...1 Accuracy timing and functional specifications in this data sheet are based on FIR_LEN 0 two PLLOUT cycles Initiation of each ADC conversion is controlled by the Multiplexer Control Circuit as descri...

Page 10: ...nal Description Section contains a chapter with a detailed description on controlling the CHOP_ENA register Temperature Sensor The 71M6403 includes an on chip temperature sensor implemented as a bandg...

Page 11: ...compensation and calibration coefficients The CE program RAM CE PRAM is loaded at boot time by the MPU and then executed by the CE Each CE instruction word is 2 bytes long The CE program counter begi...

Page 12: ...2 CE DRAM Locations for ADC Results CE Functional Overview The ADC processes one sample per channel per multiplexer cycle Figure 4 shows the timing of the six samples taken during one multiplexer cyc...

Page 13: ...its initial measurements The following diagram shows the timing delay of a CE trip indication relative to application of power and the reference clock Power Up Detection Time The T1 delay is a system...

Page 14: ...help reduce design cycle time Memory Organization The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces Memory organization in the 80515 is similar to that of th...

Page 15: ...wo types of instructions differing in whether they provide an eight bit or sixteen bit indirect address to the external data RAM In the first type MOVX A Ri the contents of R0 or R1 in the current reg...

Page 16: ...Table 4 shows the internal data memory map Address Direct addressing Indirect addressing 0xFF 0x80 Special Function Registers SFRs RAM 0x7F 0x30 Byte addressable area 0x2F 0x20 Bit addressable area 0x...

Page 17: ...egister S0CON 0x98 0x00 Serial Port 0 Control Register S0BUF 0x99 0x00 Serial Port 0 Data Buffer IEN2 0x9A 0x00 Interrupt Enable Register 2 S1CON 0x9B 0x00 Serial Port 1 Control Register S1BUF 0x9C 0x...

Page 18: ...1 RS0 Bank selected Location 00 Bank 0 0x00 0x07 01 Bank 1 0x08 0x0F 10 Bank 2 0x10 0x17 11 Bank 3 0x18 0x1F PSW 2 OV Overflow flag PSW 1 User defined flag PSW 0 P Parity flag affected by hardware to...

Page 19: ...read data through any of these ports if they are not used for alternate purposes Special Function Registers Specific to the 71M6403 Table 10 shows the location and description of the 71M6403 specific...

Page 20: ...ns on the whole WDI register should be used when writing The byte must have all bits set except the bits that are to be cleared The multi purpose register WDI contains the following bits Bit 0 IE_XFER...

Page 21: ...2 smod fCKMPU 384 256 TH1 2 smod fCKMPU 64 2 10 S0REL Serial Interface 1 N A fCKMPU 32 2 10 S1REL Note S0REL and S1REL are 10 bit values derived by combining bits from the respective timer reload regi...

Page 22: ...9 bit UART 1 0 3 9 bit UART 1 1 S0CON 5 SM20 Enables the inter processor communication feature S0CON 4 REN0 If set enables serial reception Cleared by software to disable reception S0CON 3 TB80 The 9...

Page 23: ...data bit in Mode A Set or cleared by the MPU depending on the function it performs parity check multiprocessor communication etc S1CON 2 RB81 In Modes 2 and 3 it is the 9 th data bit received In Mode...

Page 24: ...1 machine cycle Four operating modes can be selected for Timer 0 and Timer 1 Two Special Function Registers TMOD and TCON are used to select the appropriate mode Timer Counter Mode Control register T...

Page 25: ...IE1 IT1 IE0 IT0 Table 20 The TCON Register Bit Symbol Function TCON 7 TF1 The Timer 1 overflow flag is set by hardware when Timer 1 overflows This flag can be cleared by software and is automatically...

Page 26: ...ode 1 Mode 2 Timer 0 mode 0 YES YES YES Timer 0 mode 1 YES YES YES Timer 0 mode 2 Not allowed Not allowed YES Table 22 Timer Modes Timer Counter Mode Control register PCON MSB LSB SMOD Table 23 The PC...

Page 27: ...nstruction sets WDT and the second instruction sets SWDT The maximum delay allowed between setting WDT and SWDT is 12 clock cycles If this period has expired and SWDT has not been set WDT is automatic...

Page 28: ...ister are not used for watchdog control Watchdog Timer Reload Register WDTREL MSB LSB 7 6 5 4 3 2 1 0 Table 31 The WDTREL Register Bit Symbol Function WDTREL 7 7 Prescaler select bit When set the watc...

Page 29: ...pt flag is sampled once per machine cycle then samples are polled by the hardware If the sample indicates a pending interrupt when the interrupt is enabled then the interrupt request flag is set On th...

Page 30: ...isable external interrupt 6 IEN1 4 EX5 EX5 0 disable external interrupt 5 IEN1 3 EX4 EX4 0 disable external interrupt 4 IEN1 2 EX3 EX3 0 disable external interrupt 3 IEN1 1 EX2 EX2 0 disable external...

Page 31: ...terrupt 0 type control bit Table 40 The TCON Bit Functions Interrupt Request register IRCON MSB LSB EX6 IEX5 IEX4 IEX3 IEX2 Table 41 The IRCON Register Bit Symbol Function IRCON 7 IRCON 6 IRCON 5 IEX6...

Page 32: ...e MPU software The ZP8 interrupt occurs every 853 4 msec External Interrupt Connection Polarity Flag Reset 0 Digital I O High Priority see DIO_Rx automatic 1 Digital I O Low Priority see DIO_Rx automa...

Page 33: ...eived simultaneously an internal polling sequence as per Table 49 determines which request is serviced first IEN enable bits must be set to permit any of these interrupts to occur Likewise each interr...

Page 34: ...s and Vectors Table 50 shows the interrupts with their associated flags and vector addresses Interrupt Request Flag Description Interrupt Vector Address IE0 External interrupt 0 0x0003 TF0 Timer 0 int...

Page 35: ...11 LCD_FS LCD_MODE LCD_EN LCD_NUM DIO_OUT DIO_IN LCD_NUM STROBE SEG24 DIO4 SEG27 DIO7 SEG32 DIO12 SEG41 DIO21 SEG0 2 SEG3 SCLK SEG4 SSDATA SEG5 SFR SEG7 19 DIO_EEX SEG6 SRDY FAULT_PULSE Figure 6 DIO P...

Page 36: ...2 and DIO_PV 0x2008 3 In this case DIO6 and DIO7 are under CE control DIO4 and DIO5 can be configured to implement the EEPROM Interface by setting the I O RAM register DIO_EEX 0x2008 4 Physical Memor...

Page 37: ...pin The RTC consists of a counter chain and output registers The counter chain consists of seconds minutes hours day of week day of month month and year The RTC is capable of processing leap years Ea...

Page 38: ...dressed individually the LCD display can be a combination of alphanumeric digits and enunciator symbols The information to be displayed is written into the lower four bits of I O RAM registers LCD_SEG...

Page 39: ...n is pulled low all digital activity in the chip stops while analog circuits are still active Additionally all I O RAM bits are cleared Hardware Watchdog Timer In addition to the basic software watchd...

Page 40: ...es the power fault detection implemented with V1 Since there is no way in firmware to disable the WDT it is guaranteed that whatever state the MPU might find itself in it will be reset to a known stat...

Page 41: ...t sequence By observing the BUSY bit in EECTRL the MPU can determine when the transmit operation is finished i e when the BUSY bit transitions from 1 to 0 INT5 is also asserted when BUSY falls The MPU...

Page 42: ...s Emulator Port The emulator port consisting of the pins E_RST E_TCLK and E_RXTX provides control of the MPU through an external in circuit emulator The E_TBUS 3 0 pins together with the E_ISYNC BRKRQ...

Page 43: ...e pins used for the SSI are multiplexed with the LCD segment outputs as shown in Table 58 Thus the LCD should be disabled when the SSI is in use SSI Signal LCD Segment Output Pin SCLK SEG3 SSDATA SEG4...

Page 44: ...is complete The CE code is designed to tolerate sudden changes in ADC data The exact CK count when each ADC value is loaded into DRAM is shown in Figure 9 Figure 9 also shows that the two serial data...

Page 45: ...12 29 18 17 Next field is delayed while SRDY is low Figure 12 SSI Timing 16 bit Field Example External Device Delays SRDY SFR is the framing pulse Although CE words are always 32 bits the SSI interfac...

Page 46: ...Post Processor IRQ Processed Data I O RAM Configuration RAM Data Figure 13 MPU CE Data Flow CE MPU Communication Figure 14 shows the functional relationship between CE and MPU The CE is controlled by...

Page 47: ...OBE Mux Ctrl Comparator FAULT_THRESH ADC DIO6 Figure 14 MPU CE Communication Functional The MPU will wait for the CE to signal that fresh data is ready the XFER interrupt It will read the data and per...

Page 48: ...of the CHOP_EN register are described in Table 59 CHOP_EN 1 CHOP_EN 0 Function 0 0 Toggle chop signal 0 1 Reference connection positive 1 0 Reference connection reversed 1 1 Toggle chop signal Table...

Page 49: ...n of the preboot sequence the ICE can be enabled and is permitted to take control of the MPU SECURE SFR 0xB2 6 the security enable bit is reset whenever the MPU is reset Hardware associated with the b...

Page 50: ...eserved 2 VREF_DIS MPU_DIV CONFIG1 2005 RESERVED ECK_DIS FIR_LEN ADC_DIS MUX_ALT FLASH66Z MUX_E VERSION 2006 VERSION 7 0 Digital I O DIO0 2008 OPT_TXDIS DIO_EEX DIO_STR DIO_FLT DIO1 2009 DIO_R1 2 0 DI...

Page 51: ...out and contain no memory and are read by the MPU as zero RESERVED bits are in use and should not be changed This table lists only the SFR registers that are not generic 8051 SFR registers Name SFR Ad...

Page 52: ...T 2 0 2003 2 0 R Three bits containing comparator output status Bit0 comp1 Bit1 comp2 Bit2 comp3 DIO_R0 2 0 DIO_R1 2 0 DIO_R2 2 0 DIO_R3 2 0 DIO_R4 2 0 DIO_R5 2 0 DIO_R6 2 0 DIO_R7 2 0 DIO_R8 2 0 DIO_...

Page 53: ...e XFER_BUSY and the ZP8 interrupts to the MPU Note that if either interrupt is to be enabled EX6 in the 80515 must also be set FIR_LEN 2005 4 R W The length of the ADC decimation FIR filter 1 22 ADC b...

Page 54: ...0 R Interrupt inputs The MPU may read these bits to see the input to external interrupts INT0 INT1 up to INT6 These bits do not have any memory and are primarily intended for debug use LCD_BSTEN 2020...

Page 55: ...EG28 41 DIO4 7 15 SEG27 41 DIO4 6 16 SEG26 41 DIO4 5 17 SEG25 41 DIO4 18 SEG24 41 None LCD_SEG0 3 0 LCD_SEG41 3 0 2030 3 0 2059 3 0 R W LCD Segment Data Each word contains information for from 1 to 4...

Page 56: ...ow these pins are converted to the SSI function regardless of LCDEN and LCD_NUM For proper LCD operation SSI_EN must not be high when LCD_EN is high SSI_10M 2070 6 R W SSI clock speed 0 5MHz 1 10MHz S...

Page 57: ...C reserved for production test D CK38 E Reserved F Reserved RESERVED 2005 7 R W Must be zero TRIMSEL 20FD W Selects the temperature trim fuse to be read with the TRIM register TRIMM 2 0 4 TRIMBGA 5 T...

Page 58: ...byte Constants Constants used in the CE Data Memory tables are Sampling frequency FS 32768Hz 13 2520 62Hz IMAX is the external rms current corresponding to 250mV pk at the inputs I0 through I5 The sy...

Page 59: ...tal frequency of operation only 6 Programmable accumulation interval generates interrupt on DIO6 for data collection 7 Programmable FAULT_THRESH register sets over current detection to generate FAULT_...

Page 60: ...M 1 When I4SUM is set to 1 all other configuration bits for I4 are ignored Likewise the CE ignores the I4SUM bit for all channels other than I4 The NB narrow band register 0x2E allows control of the b...

Page 61: ...task in circuit breaker applications is to detect an over current situation as quickly as possible and to apply the tripping procedures The CE firmware has an integrated comparator function that help...

Page 62: ...ame Default Description 0x08 CAL_I0 16384 0x09 CAL_I1 16384 0x0A CAL_I2 16384 0x0B CAL_I3 16384 0x0C CAL_I4 16384 0x0D CAL_I5 16384 These six constants control the gain of their respective channels Th...

Page 63: ...NSI C source code The code is available as part of the Demonstration Kit for the 71M6403 The Demonstration Kits come with the 71M6403 IC preprogrammed with demo firmware mounted on a functional exampl...

Page 64: ...Input pins 5mA to 5mA 0 5V to V3P3D 0 5V Output pins 30mA to 30mA 0 5 to V3P3D 0 5V Temperature Operating junction temperature peak 100ms 140 C Operating junction temperature continuous 125 C Storage...

Page 65: ...GNDD should also be shorted on the circuit board LOGIC LEVELS PARAMETER CONDITION MIN TYP MAX UNIT Digital high level input voltage VIH 2 V3P3D V Digital low level input voltage VIL 0 3 0 8 V ILOAD 1m...

Page 66: ...rite VBAT 3 3V RTM_EN 0 ECK_DIS 1 MPU_DIV 3 0 2 0 4 mA V3P3A V3P3D current Power save sleep mode V3P3A V3P3D VLCD 3 3V ADC_DIS 1 CE_EN 0 MPU_DIV 3 6 7 mA V3P3D current Write Flash Normal Operation as...

Page 67: ...0 A 10 A 2 5 k VNOM definition 1 VNOM T VREF 22 T 22 TC1 T 22 2 TC2 V VREF temperature coefficients TC1 linear TC2 quadratic 6 68 0 341 V C V C2 VREF T deviation from VNOM T 40 22 max 10 6 T VNOM T VN...

Page 68: ...INTERFACE PARAMETER CONDITION MIN TYP MAX UNIT OPT_TX VOH V3P3D OPT_TX ISOURCE 1mA 0 4 V OPT_TX VOL ISINK 20mA 0 7 V OPT_RX Vin Threshold VinRISING VinFALLING 2 200 250 300 mV OPT_RX Vin Hysteresis V...

Page 69: ...tage LCD_FS 1F With respect to VLCD 0 2 0 V VLC0 Min Voltage LCD_FS 00 With respect to VLCD 0 7 0 2 0 2 V VLC1 Voltage 1 3 bias bias With respect to 2 VLCD 3 With respect to VLCD 2 10 10 10 10 VLC0 Vo...

Page 70: ...les 20 000 Cycles Flash data retention 25 C 100 Years FLASH MEMORY TIMING PARAMETER CONDITION MIN TYP MAX UNIT Write Time per Byte 42 s Read Time No wait states Page Erase 512 bytes 20 ms Mass Erase 2...

Page 71: ...emiconductor Corporation REV 1 0 Packaging Information 100 Pin LQFP PACKAGE OUTLINE Bottom View MAX 1 600 0 50 TYP 14 000 0 200 0 225 0 045 0 60 TYP 1 50 0 10 0 10 0 10 16 000 0 300 16 000 0 300 100 1...

Page 72: ...DA NC OPT_RX V1 V2 INEUTRAL VREF I0 I2 I1 I3 I5 V3P3A GNDA I4 GNDD SEG14 SEG13 NC SEG12 SEG11 NC NC NC NC SEG10 SEG9 SEG7 MUX_SYNC SEG8 NC SEG6 SRDY SEG36 DIO16 NC SEG35 DIO15 SEG34 DIO14 E_ISYNC BRKR...

Page 73: ...D power supply The DC source for the LCD driver circuitry is connected here NC 32 33 36 42 43 44 47 55 90 95 No Connect Analog Pins NAME PIN TYPE DESCRIPTION I0 I1 I2 I3 I4 I5 84 80 83 79 82 78 I Line...

Page 74: ...operation this pin is set to 1 To reset the chip this pin is driven to 0 This pin has an internal 30 A nominal current source pull up but no Schmitt trigger input circuitry The minimum width of the p...

Page 75: ...roduct The data sheet is subject to change TSC assumes no obligation regarding future manufacture unless agreed to in writing If and when manufactured and sold this product is sold subject to the term...

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