71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 11 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
Functional Description
The AFE functions as a data acquisition system, controlled by the MPU. The main signals (I0, I3, I1, I4, I2, I5) are sampled and
the ADC counts obtained are stored in CE RAM where they can be accessed by the CE and, if necessary, by the MPU.
I0
I1
I2
I3
MUX
VREF
VBIAS
I4
TEMP
CK32
VREF
VREF_DIS
MUX
CTRL
MUX_DIV
CHOP_EN
I5
MUX_ALT
V3P3A
FIR_LEN
FIR
FILTER
∆Σ
ADC
CONVERTER
+
-
VREF
VBIAS
INEUTRAL
Figure 3: AFE Block Diagram
Computation Engine (CE)
The CE, a dedicated 32-bit RISC processor, performs the precision computations necessary to accurately measure currents.
The CE calculations and processes include:
•
Scaling of the processed samples based on chip temperature (temperature compensation) and calibration coefficients.
The CE program RAM (CE PRAM) is loaded at boot time by the MPU and then executed by the CE. Each CE instruction word is
2 bytes long. The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code pass
ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the multiplexer cycle
ends (see System Timing Summary in the Functional Description Section).
The CE data RAM (CE DRAM) is shared by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time slots are
reserved for FIR, RTM, and MPU, respectively, such that memory accesses to CE_RAM do not collide. Holding registers are
used to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed, depending on
the frequency of CKMPU.
Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE.
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