SoCKit User Manual
40
www.terasic.com
December 1, 2015
HPS_DDR3_DQ[6] PIN_J30
HPS
DDR3 Data[6]
SSTL-15 Class I
HPS_DDR3_DQ[7] PIN_J29
HPS
DDR3 Data[7]
SSTL-15 Class I
HPS_DDR3_DQ[8]
PIN_K26
HPS DDR3 Data[8]
SSTL-15 Class I
HPS_DDR3_DQ[9]
PIN_L26
HPS DDR3 Data[9]
SSTL-15 Class I
HPS_DDR3_DQ[10]
PIN_K29
HPS DDR3 Data[10]
SSTL-15 Class I
HPS_DDR3_DQ[11]
PIN_K27
HPS DDR3 Data[11]
SSTL-15 Class I
HPS_DDR3_DQ[12]
PIN_M26
HPS DDR3 Data[12]
SSTL-15 Class I
HPS_DDR3_DQ[13]
PIN_M27
HPS DDR3 Data[13]
SSTL-15 Class I
HPS_DDR3_DQ[14]
PIN_L28
HPS DDR3 Data[14]
SSTL-15 Class I
HPS_DDR3_DQ[15]
PIN_M30
HPS DDR3 Data[15]
SSTL-15 Class I
HPS_DDR3_DQ[16]
PIN_U26
HPS DDR3 Data[16]
SSTL-15 Class I
HPS_DDR3_DQ[17]
PIN_T26
HPS DDR3 Data[17]
SSTL-15 Class I
HPS_DDR3_DQ[18]
PIN_N29
HPS DDR3 Data[18]
SSTL-15 Class I
HPS_DDR3_DQ[19]
PIN_N28
HPS DDR3 Data[19]
SSTL-15 Class I
HPS_DDR3_DQ[20] PIN_P26
HPS
DDR3 Data[20]
SSTL-15 Class I
HPS_DDR3_DQ[21] PIN_P27
HPS
DDR3 Data[21]
SSTL-15 Class I
HPS_DDR3_DQ[22]
PIN_N27
HPS DDR3 Data[22]
SSTL-15 Class I
HPS_DDR3_DQ[23]
PIN_R29
HPS DDR3 Data[23]
SSTL-15 Class I
HPS_DDR3_DQ[24] PIN_P24
HPS
DDR3 Data[24]
SSTL-15 Class I
HPS_DDR3_DQ[25] PIN_P25
HPS
DDR3 Data[25]
SSTL-15 Class I
HPS_DDR3_DQ[26]
PIN_T29
HPS DDR3 Data[26]
SSTL-15 Class I
HPS_DDR3_DQ[27]
PIN_T28
HPS DDR3 Data[27]
SSTL-15 Class I
HPS_DDR3_DQ[28]
PIN_R27
HPS DDR3 Data[28]
SSTL-15 Class I
HPS_DDR3_DQ[29]
PIN_R26
HPS DDR3 Data[29]
SSTL-15 Class I
HPS_DDR3_DQ[30] PIN_V30
HPS
DDR3 Data[30]
SSTL-15 Class I
HPS_DDR3_DQ[31]
PIN_W29
HPS DDR3 Data[31]
SSTL-15 Class I
HPS_DDR3_DQS_n[0]
PIN_M19
HPS DDR3 Data Strobe n[0]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_n[1]
PIN_N24
HPS DDR3 Data Strobe n[1]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_n[2]
PIN_R18
HPS DDR3 Data Strobe n[2]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_n[3]
PIN_R21
HPS DDR3 Data Strobe n[3]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_p[0]
PIN_N18
HPS DDR3 Data Strobe p[0]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_p[1]
PIN_N25
HPS DDR3 Data Strobe p[1]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_p[2]
PIN_R19
HPS DDR3 Data Strobe p[2]
Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_p[3]
PIN_R22
HPS DDR3 Data Strobe p[3]
Differential 1.5-V SSTL Class I
HPS_DDR3_ODT
PIN_H28
HPS DDR3 On-die Termination
SSTL-15 Class I
HPS_DDR3_RAS_n
PIN_D30
DDR3 Row Address Strobe
SSTL-15 Class I
HPS_DDR3_RESET_n PIN_P30
HPS DDR3 Reset
SSTL-15 Class I
HPS_DDR3_WE_n PIN_C28 HPS
DDR3 Write Enable
SSTL-15 Class I
HPS_DDR3_RZQ
PIN_D27
External reference ball for
output drive calibration
1.5 V
3
3
.
.
7
7
.
.
5
5
Q
Q
S
S
P
P
I
I
F
F
l
l
a
a
s
s
h
h
The board supports a 512M-bit serial NOR flash device for non-volatile storage of HPS boot code,
