SoCKit User Manual
41
www.terasic.com
December 1, 2015
user data and program. The device is connected to HPS dedicated interface. It may contain
secondary boot code.
This device has a 4-bit data interface and uses 3.3V CMOS signaling standard. Connections
between Cyclone V SoC FPGA and Flash are shown in
Figure 3-24
.
To program the QSPI flash, the
HPS Flash Programmer
is provided both as part of the Altera
Quartus II suite and as part of the free Altera Quartus II Programmer. The HPS Flash Programmer
sends file contents over an Altera download cable, such as the USB Blaster II, to the HPS, and
instructs the HPS to write the data to the flash memory.
Figure 3-24 Connections Between Cyclone V SoC FPGA and QSPI Flash
Table 3-26
below summarizes the pins on the flash device. Signal names are from the device datasheet and
directions are relative to the Cyclone V SoC FPGA.
Table 3-26 QSPI Flash Interface I/O
Signal Name
FPGA Pin No.
Description
I/O Standard
HPS_FLASH_DATA[0]
PIN_C20
HPS FLASH Data[0]
3.3V
HPS_FLASH_DATA[1]
PIN_H18
HPS FLASH Data[1]
3.3V
HPS_FLASH_DATA[2]
PIN_A19
HPS FLASH Data[2]
3.3V
HPS_FLASH_DATA[3] PIN_E19
HPS FLASH Data[3]
3.3V
HPS_FLASH_DCLK
PIN_D19
HPS FLASH Data Clock
3.3V
HPS_FLASH_NCSO PIN_A18
HPS FLASH Chip Enable
3.3V
3
3
.
.
7
7
.
.
6
6
M
M
i
i
c
c
r
r
o
o
S
S
D
D
The board supports Micro SD card interface using x4 data lines. And it may contain secondary boot
code for HPS.
Figure 3-25
shows the related signals.
Finally,
Table 3-27
lists all the associated pins for interfacing HPS respectively.
