SoCKit User Manual
61
www.terasic.com
December 1, 2015
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Many applications use a high performance RAM, such as a DDR3 SDRAM, to provide temporary
storage. In this demonstration hardware and software designs are provided to illustrate how to
perform DDR3 memory access in QSYS. We describe how the Altera’s “DDR3 SDRAM Controller
with UniPHY” IP is used to access a DDR3-SDRAM, and how the Nios II processor is used to read
and write the SDRAM for hardware verification. The DDR3 SDRAM controller handles the
complex aspects of using DDR3 SDRAM by initializing the memory devices, managing SDRAM
banks, and keeping the devices refreshed at appropriate intervals.
System Block Diagram
Figure 5-6
shows the system block diagram of this demonstration. The system requires a 50 MHz
clock provided from the board. The DDR3 controller is configured as a 1 GB DDR3-300 controller.
The DDR3 IP generates one 300 MHz clock as SDRAM’s data clock and one half-rate system clock
150 MHz for those host controllers, e.g. Nios II processor, accessing the SDRAM. In the QSYS,
Nios II and the On-Chip Memory are designed running with the 100MHz clock, and the Nios II
program is running in the on-chip memory.
Figure 5-6 Block diagram of the DDR3 Basic Demonstration
The system flow is controlled by a Nios II program. First, the Nios II program writes test patterns
into the whole 1 GB of SDRAM. Then, it calls Nios II system function, alt_dache_flush_all, to
make sure all data has been written to SDRAM. Finally, it reads data from SDRAM for data
