SoCKit User Manual
48
www.terasic.com
December 1, 2015
The top-level design file contains top-level Verilog HDL wrapper for users to add their own
design/logic. The Quartus II setting file contains information such as FPGA device type, top-level
pin assignment, and the I/O standard for each user-defined I/O pin.
Finally, the Quartus II programmer must be used to download SOF file to the development board
using a JTAG interface.
Figure 4-1 The general design flow of building a design
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This section provides the detailed procedures on how the SoCKit System Builder is used.
Install and launch the SoCKit System Builder
The SoCKit System Builder is located in the directory:
“Tools\SOC_Kit_system_builder”
on the SoCKit System CD. Users can copy the whole folder to a
host computer without installing the utility. Launch the SoCKit System Builder by executing the
SOC_Kit_SystemBuilder.exe on the host computer and the GUI window will appear as shown in
Figure 4-2
.
