SoCKit User Manual
62
www.terasic.com
December 1, 2015
verification. The program will show progress in JTAG-Terminal when writing/reading data to/from
the SDRAM. When verification process is completed, the result is displayed in the JTAG-Terminal.
Altera DDR3 SDRAM Controller with UniPHY
To use Altera DDR3 controller, users need to perform the four major steps:
1.
Create correct pin assignments for DDR3.
2.
Setup correct parameters in DDR3 controller dialog.
3.
Perform “Analysis and Synthesis” by clicking Quartus menu: Process
Start
Start
Analysis & Synthesis.
4.
Run the TCL files generated by DDR3 IP by clicking Quartus menu: Tools
TCL Scripts…
Design Tools
Quartus II 13.1
Nios II Eclipse 13.1
Demonstration Source Code
Quartus Project directory: SoCKit_DDR3_Nios_Test
Nios II Eclipse:
SoCKit_DDR3_Nios_Test\Software
Nios II Project Compilation
Before you attempt to compile the reference design under Nios II Eclipse, make sure the project is
cleaned first by clicking ‘Clean’ from the ‘Project’ menu of Nios II Eclipse.
Demonstration Batch File
Demo Batch File Folder:
SoCKit_DDR3_Nios_Test\demo_batch
The demo batch file includes following files:
Batch File for USB-Blaster (II) : SoCKit_DDR3_Nios_Test.bat,
SoCKit_DDR3_Nios_Test_bashrc
FPGA Configure File : SoCKit_DDR3_Nios_Test
.sof
Nios II Program: SoCKit_DDR3_Nios_Test
.elf
Demonstration Setup
Make sure Quartus II and Nios II are installed on your PC.
