SoCKit User Manual
32
www.terasic.com
December 1, 2015
Figure 3-19 Connection between FPGA and IR
Table 3-18 Pin Assignments for IR
Signal Name
FPGA Pin No.
Description
I/O Standard
IRDA_RXD PIN_
AH2
IR Receiver
3.3V
3.6.6
DDR3 Memory on FPGA
The board supports 1GB of DDR3 SDRAM comprising of two x16 bit DDR3 devices on FPGA
side. The DDR3 devices shipped with this board are running at 400MHz if the hard external
memory interface is enabled, and at 300MHz if the hard external memory interface if not enabled.
Figure 3-20
shows the connections between the DDR3 and Cyclone V SoC FPGA.
Table 3-19
shows the DDR3 interface pin assignments.
Figure 3-20 Connections between FPGA and DDR3