SoCKit User Manual
27
www.terasic.com
December 1, 2015
HSMC_TX _n[4]
PIN_C4
LVDS TX bit 4n or CMOS I/O
Depend on JP2
HSMC_TX _n[5]
PIN_E2
LVDS TX bit 5n or CMOS I/O
Depend on JP2
HSMC_TX _n[6]
PIN_D4
LVDS TX bit 6n or CMOS I/O
Depend on JP2
HSMC_TX _n[7]
PIN_B3
LVDS TX bit 7n or CMOS I/O
Depend on JP2
HSMC_TX _n[8]
PIN_D1
LVDS TX bit 8n or CMOS I/O
Depend on JP2
HSMC_TX _n[9]
PIN_C2
LVDS TX bit 9n or CMOS I/O
Depend on JP2
HSMC_TX _n[10]
PIN_B1
LVDS TX bit 10n or CMOS I/O
Depend on JP2
HSMC_TX _n[11]
PIN_A3
LVDS TX bit 11n or CMOS I/O
Depend on JP2
HSMC_TX _n[12]
PIN_A5
LVDS TX bit 12n or CMOS I/O
Depend on JP2
HSMC_TX _n[13]
PIN_B7
LVDS TX bit 13n or CMOS I/O
Depend on JP2
HSMC_TX _n[14]
PIN_B8
LVDS TX bit 14n or CMOS I/O
Depend on JP2
HSMC_TX _n[15]
PIN_B11
LVDS TX bit 15n or CMOS I/O
Depend on JP2
HSMC_TX _n[16]
PIN_A13
LVDS TX bit 16n or CMOS I/O
Depend on JP2
HSMC_TX _p[0]
PIN_A9
LVDS TX bit 0 or CMOS I/O
Depend on JP2
HSMC_TX _p[1]
PIN_E8
LVDS TX bit 1 or CMOS I/O
Depend on JP2
HSMC_TX _p[2]
PIN_G7
LVDS TX bit 2 or CMOS I/O
Depend on JP2
HSMC_TX _p[3]
PIN_D6
LVDS TX bit 3 or CMOS I/O
Depend on JP2
HSMC_TX _p[4]
PIN_D5
LVDS TX bit 4 or CMOS I/O
Depend on JP2
HSMC_TX _p[5]
PIN_E3
LVDS TX bit 5 or CMOS I/O
Depend on JP2
HSMC_TX _p[6]
PIN_E4
LVDS TX bit 6 or CMOS I/O
Depend on JP2
HSMC_TX _p[7]
PIN_C3
LVDS TX bit 7 or CMOS I/O
Depend on JP2
HSMC_TX _p[8]
PIN_E1
LVDS TX bit 8 or CMOS I/O
Depend on JP2
HSMC_TX _p[9]
PIN_D2
LVDS TX bit 9 or CMOS I/O
Depend on JP2
HSMC_TX _p[10]
PIN_B2
LVDS TX bit 10 or CMOS I/O
Depend on JP2
HSMC_TX _p[11]
PIN_A4
LVDS TX bit 11 or CMOS I/O
Depend on JP2
HSMC_TX _p[12]
PIN_A6
LVDS TX bit 12 or CMOS I/O
Depend on JP2
HSMC_TX _p[13]
PIN_C7
LVDS TX bit 13 or CMOS I/O
Depend on JP2
HSMC_TX _p[14]
PIN_C8
LVDS TX bit 14 or CMOS I/O
Depend on JP2
HSMC_TX _p[15]
PIN_C12
LVDS TX bit 15 or CMOS I/O
Depend on JP2
HSMC_TX _p[16]
PIN_B13
LVDS TX bit 16 or CMOS I/O
Depend on JP2
3.6.3
Audio CODEC
The board provides high-quality 24-bit audio via the Analog Devices SSM2603 audio CODEC
(Encoder/Decoder). This chip supports microphone-in, line-in, and line-out ports, with a sample rate
adjustable from 8 kHz to 96 kHz. The SSM2603 is controlled via a serial I2C bus interface, which
is connected to pins on the Cyclone V SoC FPGA. A schematic diagram of the audio circuitry is
shown in
Figure 3-16
. Detailed information for using the SSM2603 codec is available in its
datasheet, which can be found on the manufacturer’s website, or in the Datasheets\Audio CODEC
folder on the SoCKit System CD
