SoCKit User Manual
24
www.terasic.com
December 1, 2015
3.6.2
HSMC connector
The board contains a High Speed Mezzanine Card (HSMC) interface to provide a mechanism for
extending the peripheral-set of an FPGA host board by means of add-on daughter cards, which can
address today’s high speed signaling requirements as well as low-speed device interface support.
The HSMC interface support JTAG, clock outputs and inputs, high-speed serial I/O (transceivers),
and single-ended or differential signaling. Signals on the HSMC port are shown in
Figure 3-15
.
Table 3-12
shows the maximum power consumption of the daughter card that connects to HSMC
port.
Figure 3-15 HSMC Signal Bank Diagram
Table 3-12 Power Supply of the HSMC
Supplied Voltage
Max. Current Limit
12V 1A
3.3V 1.5A
Table 3-13 Pin Assignments for HSMC connector
Signal Name
FPGA Pin No.
Description
I/O Standard
HSMC_CLK_IN0
PIN_J14
Dedicated clock input
Depend on JP2
HSMC_CLKIN_n1
PIN_AB27
LVDS RX or CMOS I/O or
differential clock input
Depend on JP2
