SoCKit User Manual
59
www.terasic.com
December 1, 2015
5
5
.
.
3
3
D
D
D
D
R
R
3
3
S
S
D
D
R
R
A
A
M
M
T
T
e
e
s
s
t
t
This demonstration presents a memory test function on the bank of DDR3-SDRAM on the SoCKit
board. The memory size of the DDR3 SDRAM bank is 1GB.
Function Block Diagram
Figure 5-5
shows the function block diagram of this demonstration. The controller uses 50 MHz as
a reference clock, generates one 300 MHz clock as memory clock, and generates one half-rate
system clock 150MHz for the controller itself.
Figure 5-5 Block Diagram of the DDR3 SDRAM (1G) Demonstration
RW_test modules read and write the entire memory space of the DDR3 through the Avalon
interface of the controller. In this project, the Avalon bus read/write test module will first write the
entire memory and then compare the read back data with the regenerated data (the same sequence as
the write data). KEY0 will trigger test control signals for the DDR3, and the LEDs will indicate the
test results according to
Table 5-3
.
Altera DDR3 SDRAM Controller with UniPHY
To use the Altera DDR3 controller, users need to perform three major steps:
1.
Create correct pin assignments for the DDR3.
2.
Setup correct parameters in DDR3 controller dialog.
3.
Perform “Analysis and Synthesis” by selecting from the Quartus II menu:
Process
Start
Start Analysis & Synthesis.
4.
Run the TCL files generated by DDR3 IP by selecting from the Quartus II menu:
