SoCKit User Manual
20
www.terasic.com
December 1, 2015
Figure 3-9 Programming a Quad Serial Configuration Device with the SFL Solution
Note: Before programming the quad serial configuration device, please set the FPGA
configuration mode switch (SW6) to ASx4 mode.
3
3
.
.
5
5
C
C
l
l
o
o
c
c
k
k
C
C
i
i
r
r
c
c
u
u
i
i
t
t
s
s
Figure 3-10
is a diagram showing the default frequencies of all of the external clocks going to the
Cyclone V SoC FPGA.
Figure 3-10 Block diagram of the clock distribution
