SoCKit User Manual
28
www.terasic.com
December 1, 2015
Figure 3-16 Connections between FPGA and Audio CODEC
Table 3-14 Pin Assignments for Audio CODEC
Signal Name
FPGA Pin No.
Description
I/O Standard
AUD_ADCLRCK
PIN_AG30
Audio CODEC ADC LR Clock
3.3V
AUD_ADCDAT PIN_AC27
Audio
CODEC
ADC
Data
3.3V
AUD_DACLRCK
PIN_AH4
Audio CODEC DAC LR Clock
3.3V
AUD_DACDAT
PIN_AG3
Audio CODEC DAC Data
3.3V
AUD_XCK
PIN_AC9
Audio CODEC Chip Clock
3.3V
AUD_BCLK
PIN_AE7
Audio CODEC Bit-Stream Clock
3.3V
AUD_I2C_SCLK PIN_AH30
I2C
Clock
3.3V
AUD_I2C_SDAT PIN_AF30
I2C
Data
3.3V
AUD_MUTE
PIN_AD26
DAC Output Mute, Active Low
3.3V
3.6.4
VGA
The board includes a 15-pin D-SUB connector for VGA output. The VGA synchronization signals
are provided directly from the Cyclone V SoC FPGA, and the Analog Devices ADV7123 triple
10-bit high-speed video DAC (only the higher 8-bits are used) is used to produce the analog data
signals (red, green, and blue). It could support the SXGA standard (1280*1024) with a bandwidth
of 100MHz.
Figure 3-17
gives the associated schematic
.
