Tektronix DSA8200 Series, Service Manual

Page: 39 / 196

Theory of Operation
DSA8200 Digital Serial Analyzer and Modules Service Manual
2- 5
module remains functional for monitoring the primary step and its reflected
components. The sampling module provides two self-contained TDR channels.
The polarity of the output step can be selected independently for each channel.
This allows differential or common mode testing of two coupled lines as well as
independent testing of isolated lines.
For major functional circuit blocks refer to Figure 5--2 on page 5--3.
Optical Sampling Modules Overview
80CXX and 80CXX-CR optical modules share the same mechanical package and
are built with a common circuit board. Different functionality within the modules
(current and future modules) is achieved by installing different O/E modules,
filters and clock recovery boards along with setting the sampler bandwidth as
demanded. The key features supported in the module are:
1
A one channel, low noise, adjustable bandwidth sampler allowing multiple
bandwidth settings for optimizing noise versus bandwidth demands.
1
An amplified or non-amplified O/E converter.
1
Support for internal RF switches in the signal path with a straight-through
path and three hardware-filtered reference receiver paths between the O/E
converter and the sampler.
1
An average optical power meter.
1
Integral clock recovery option with internal coaxial connection to the
mainframe trigger, front panel clock and data output (not all have data).
1
Communication with the mainframe for identification, control and calibra-
tion/compensation storage.
The “system response” depends on all of the components in the signal path from
the front panel to the sampler. Bandwidth and reference receiver responses are
calibrated at the factory with a sub-picosecond optical impulse applied to the
front panel connector or with an optical heterodyne system. This ensures that all
components are included, but also means that components can not be replaced
without performing calibration.
Compensation performs a DC transfer curve characterization for each bandwidth/
reference receiver setting. The curve data is stored in the module’s EEPROM and
used to generate a look-up table in the mainframe. This data corrects for
linearity, gain and offset errors in the sampler.
Reference receivers can be created in any of the following ways:
1
A hardware filter inserted between the O/E and the sampler and dominates
the response.