Tektronix DSA8200 Series, Service Manual

Page: 38 / 196

Theory of Operation
2- 4
DSA8200 Digital Serial Analyzer and Modules Service Manual
Most electrical channels feature a Tekprobe Level 2 probe power connector for
attachment of a real time probe. The control of this probe is a mainframe
function.
All module calibration signals are derived from a 2.5 V precision voltage
reference internal to the sampling module. Settings derived from this reference
are stored in a non-volatile EEPROM in the sampling module, although the
responsibility for the execution of these settings is with the mainframe.
For major functional circuit blocks refer to Figure 5--2 on page 5--3.
The TDR/Sampling modules are low noise samplers, with each channel capable
of generating its own Time Domain Reflectometry (TDR) step. The basic
features of these modules are listed in the following table.
Table 2- 2: TDR sampling module features
Feature 80E04 80E08 80E10
Number of independent channels 2 2 2
Number of TDR channels 2 2 2
Bandwidth 20 GHz 30 GHz 50 GHz
Selectable bandwidths N.A. 20 GHz, 30 GHz 40 GHz, 30 GHz, 50 GHz
Signal connectors 3.5 mm female 2.92 mm (K) female 1.85 mm (V) female
Remote sampler N.A. 2 meter cable 2 meter cable
For these modules, a single strobe delivered from the instrument mainframe to
both acquisition channels controls the timing of the strobe assertion to both
channels. If channel-to-channel deskew is zero and the channel delays (if
equipped) are matched, the sampling coincidence between channels is very close.
Acquisition deskew function is carried out by making separate acquisitions over
acquisition windows or by adjusting Channel Delay (if equipped).
Each electrical channel features a Tekprobe Level 2 probe power connector for
attachment of a real time probe. The control of this probe is a mainframe
function.
All module calibration signals are derived from a 2.5 V precision voltage
reference internal to the sampling module. Settings derived from this reference
are stored in a non-volatile EEPROM in the sampling module, although the
responsibility for the execution of these settings is with the mainframe.
When used in the acquisition mode (that is, with the TDR step generator turned
off) each channel functions as a normal sampling input. In the TDR mode, a fast
rise time step is generated internally for each channel and applied to the input
signal path for that channel. The acquisition portion of the TDR/sampling
80E04, 80E08, and 80E10
TDR/Sampling Modules