SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 66
Version 1.1
3.4 SYSTEM CONTROL REGISTERS 1
Base Address: 0x4005 E000
3.4.1 AHB Clock Enable register (SYS1_AHBCLKEN)
Address Offset: 0x00
The SYS_AHBCLKEN register enables the AHB clock to individual system and peripheral blocks.
Note:
1. When the clock is disabled, the peripheral register values may not be readable by SW and the value
returned is always 0x0.
2. HW will replace GPIO with CLKOUT function directly if CLKOUTSEL is Not 0.
3. User shall disable the AHB clock for individual peripheral to decrease power consumption by
demand.
Bit
Name
Description
Attribute
Reset
31
Reserved
R
0
30:28
CLKOUTSEL[2:0]
Clock output source
000: Disable
001: ILRC clock
010: ELS clock
100: HCLK
101: IHRC clock
110: EHS clock
111: PLL clock output
Other: Disable
R/W
0
27
CRCCLKEN
Enables clock for CRC.
0: Disable
1: Enable
R/W
0
26
LCDCLKEN
Enables clock for LCD
0: Disable
1: Enable
R/W
0
25
I2S1CLKEN
Enables clock for I2S1.
0: Disable
1: Enable
R/W
0
24
WDTCLKEN
Enables clock for WDT.
0: Reserved
1: Enable
R/W
1
23
RTCCLKEN
Enables clock for RTC.
0: Disable
1: Enable
R/W
0
22
I2S0CLKEN
Enables clock for I2S0.
0: Disable
1: Enable
R/W
0
21
I2C0CLKEN
Enables clock for I2C0.
0: Disable
1: Enable
R/W
0
20
I2C1CLKEN
Enables clock for I2C1.
0: Disable
1: Enable
R/W
0
19
UART3CLKEN
Enables clock for UART3.
0: Disable
1: Enable
R/W
0
18
UART2CLKEN
Enables clock for UART2.
0: Disable
1: Enable
R/W
0
17
UART1CLKEN
Enables clock for UART1.
0: Disable
1: Enable
R/W
0
