SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 68
Version 1.1
Other: Reserved
15:0
Reserved
R
0
3.4.3 APB Clock Prescale register 1 (SYS1_APBCP1)
Address Offset: 0x08
Note: Must reset the corresponding peripheral with SYS1_PRST register after changing the prescale
value.
Bit
Name
Description
Attribute
Reset
31
Reserved
R
0
30:28
CLKOUTPRE[2:0]
Clock-out source prescaler
000: Clock-out source / 1
001: Clock-out source / 2
010: Clock-out source / 4
011: Clock-out source / 8
100: Clock-out source / 16
101: Clock-out source / 32
110: Clock-out source / 64
111: Clock-out source / 128
R/W
0
27
Reserved
R
0
26:24
I2C1PRE[2:0]
I2C1 clock source prescaler
000: HCLK / 1
001: HCLK / 2
010: HCLK / 4
011: HCLK / 8
100: HCLK / 16
Other: Reserved
W
0
23
Reserved
R
0
22:20
WDTPRE[2:0]
WDT clock source prescaler
000: WDT_PCLK = WDT clock source / 1
001: WDT_PCLK = WDT clock source / 2
010: WDT_PCLK = WDT clock source / 4
011: WDT_PCLK = WDT clock source / 8
100: WDT_PCLK = WDT clock source / 16
101: WDT_PCLK = WDT clock source / 32
Other: Reserved
R/W
0
19:18
Reserved
R
0
17:15
I2S1PRE[2:0]
I2S1 clock source prescaler
000: HCLK / 1
001: HCLK / 2
010: HCLK / 4
011: HCLK / 8
100: HCLK / 16
111: HCLK / 3
Other: Reserved
R/W
0
14:12
I2S0PRE[2:0]
I2S0 clock source prescaler
000: HCLK / 1
001: HCLK / 2
010: HCLK / 4
011: HCLK / 8
100: HCLK / 16
111: HCLK / 3
Other: Reserved
R/W
0
11
Reserved
R
0
