SONIX SN32F280 Series, User Manual

Page: 175 / 268

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 175
Version 1.1
The auto-baud interrupts have to be cleared by setting the corresponding ABTOINTCLR and ABEOIE bits in UARTn_IE
register.
The fractional baud rate generator must be disabled (DIVADDVAL = 0) during auto-baud. Also, when auto-baud is used,
any write to
UARTn_DLM and UARTn_DLL registers should be done before UARTn_ABCCTRL register write. The
minimum and the maximum baud rates supported by UART are a function of UARTn_PCLK and the number of data bits,
stop bits and parity bits.
15.6.2 AUTO-BAUD MODES
When the SW is expecting an “AT” command, it configures the UART with the expected character format and sets the
ACR Start bit. The initial values in the divisor latches DLM and DLM don‘t care. Because of the “A” or “a” ASCII coding
(“A” = 0x41, “a” = 0x61), the UART Rx pin sensed start bit and the LSB of the expected character are delimited by two
falling edges. When the ACR Start bit is set, the auto-baud protocol will execute the following phases:
1.
On START bit setting, the baud rate measurement counter is reset and the RSR is reset. The RSR baud rate is
switched to the highest rate.
2. A falling edge on URXD pin triggers the beginning of the start bit. The rate measuring counter will start counting
UARTn_PCLK cycles.
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with the frequency of the UART
input clock, guaranteeing the start bit is stored in the RSR.
4. During the receipt of the start bit (and the character LSB for MODE = 0 in UARTn_ABCTRL register), the rate
counter will continue incrementing with the pre-scaled UART input clock (UARTn_PCLK).
5. If MODE = 0, the rate counter will stop on next falling edge of the UART RX pin. If MODE = 1, the rate counter will
stop on the next rising edge of the URXD pin.
6. The rate counter is loaded into UARTn_DLM / UARTn_DLL and the baud rate will be switched to normal operation.
After setting the DLM/DLL, the end of auto-baud interrupt ABEOINT in UARTn_II register will be set, if enabled.
The RSR will now continue receiving the remaining bits of the character.

AUTO-BAUD RATE MODE 0 Waveform
bit1 bit3 bit4 bit5 bit6 Start bit7 Parity Stop
URXD
bit0 bit2
“A” (0x41) or “a” (0x61)
START bit in
USARTn_ABCTRL
Start bit LSB of “A” or “a”
Rate Counter
16 x Baud Rate
16 Cycles 16 Cycles

AUTO-BAUD RATE MODE 1 Waveform