SONIX SN32F280 Series, User Manual

Page: 177 / 268

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 177
Version 1.1
15.7 UART REGISTERS
Base Address: 0x4001 6000 (UART0)
0x4005 6000 (UART1)
0x4005 4000 (UART2)
0x4005 2000 (UART3)
15.7.1 UART n Receiver Buffer register (UARTn_RB) (n=0,1,2,3)
Address Offset: 0x00
This register is the byte of the UART RX FIFO, and contains the character received and can be read via the bus
interface. The LSB (bit 0) contains the first-received data bit. If the character received is less than 8 bits, the unused
MSBs are padded with zeros.
The Divisor Latch Access Bit (DLAB) in the UARTn_LC register must be zero in order to access this register.
Since PE, FE and BI bits correspond to the byte on the top of the UART RX FIFO (i.e. the one that will be read in the
next read from this register), the right approach for fetching the valid pair of received byte and its status bits is first t o
read the content of the
UARTn_LS register, and then to read a byte from this register.
Bit Name Description Attribute Reset
31:8
Reserved R 0
7:0 RB[7:0]
Contains the received byte in the UART RX FIFO.
R 0
15.7.2 UART n Transmitter Holding register (UARTn_TH) (n=0,1,2,3)
Address Offset: 0x00
This register is the byte of the UART TX FIFO. The byte is the character in the TX FIFO and can be written via the bus
interface. The LSB represents the first bit to transmit.
The Divisor Latch Access Bit (DLAB) in
UARTn_LC register must be zero in order to access this register.
Bit Name Description Attribute Reset
31:8 Reserved R 0
7:0
TH[7:0]
The byte will be sent when it is the byte in TX FIFO and the transmitter is
available.
W 0
15.7.3 UART n Divisor Latch LSB registers (UARTn_DLL) (n =0,1,2,3)
Address Offset: 0x00
The UART Divisor Latch is part of the UART Baud Rate Generator and holds the value used (optionally with the
Fractional Divider) to divide the UARTn_PCLK clock in order to produce the baud rate clock, which must be the multiple
of the desired baud rate that is specified by the Oversampling Register (typically 16X).
The UARTn_DLL and UARTn_DLM registers together form a 16-bit divisor, and DLAB bit in
UARTn_LC register must
be one in order to access these registers.
DLL contains the lower 8 bits of the divisor and DLM contains the higher 8 bits. A zero value is treated like 0x0001.
Bit Name Description Attribute Reset
31:8 Reserved R 0
7:0 DLL[7:0]
The UART Divisor Latch LSB Register, along with the DLM register,
determines the baud rate of the UART.
R/W 0