SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 180
Version 1.1
0: Disable parity generation and checking.
1: Enable parity generation and checking.
2
SBS
Stop Bit Select bit
0: 1 stop bit.
1: 2 stop bits (1.5 if WLS bits=00)
R/W
0
1:0
WLS[1:0]
Word Length Select bits
00: 5-bit character length.
01: 6-bit character length.
10: 7-bit character length.
11: 8-bit character length.
R/W
0
15.7.8 UART n Line Status register (UARTn_LS) (n=0,1,2,3)
Address Offset: 0x14
Note:
The
break interrupt (BI) is associated with the character in the UARTn_RB FIFO.
The
framing error (FE) is associated with the character inthe UARTn_RB FIFO.
The
parity error (PE) is associated with the character in the UARTn_RB FIFO.
Bit
Name
Description
Attribute
Reset
31:8
Reserved
R
0
7
RXFE
Error in RX FIFO flag.
RXFE =1 when a character with a RX error such as framing error, parity
error, or break interrupt, is loaded into the UARTn_RB register. This bit is
cleared when the UARTn_LS register is read and there are no subsequent
errors in the UART FIFO.
0: UARTn_RB register contains no UART RX errors or FIFOEN=0
1: UARTn_RB register contains at least one UART RX error.
R
0
6
TEMT
Transmitter Empty flag
TEMT=1 when both THR and TSR are empty; TEMT is cleared when either
the TSR or the THR contain valid data.
0: THR and/or TSR contains valid data.
1: THR and TSR are empty.
R
1
5
THRE
Transmitter Holding Register Empty flag
THRE indicates that the UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to issue THRE interrupt
to if THREIE=1. THRE=1 when a character is transferred from the THR into
the TSR. The bit is reset to logic 0 concurrently with the loading of the
Transmitter Holding Register by the CPU.
0: THR contains valid data.
1: THR (TX FIFO) is empty.
R
1
4
BI
Break Interrupt flag.
When RXD1 is held in the spacing state (all zeros) for one full character
transmission (start, data, parity, stop), a break interrupt occurs. Once the
break condition has been detected, the receiver goes idle until RXD1 goes
to marking state (all ones). A UARTn_LS register read clears BI bit. The
time of break detection is dependent on FIFOEN bit in UARTn_FIFOCTRL
register.
0: Break interrupt status is inactive.
1: Break interrupt status is active.
R
0
3
FE
Framing Error flag.
When the stop bit of a received character is a logic 0, a framing error
occurs. A UARTn_LS register read clears FE bit. The time of the framing
error detection is dependent on FIFOEN bit in UARTn_FIFOCTRL register.
Upon detection of a framing error, the RX will attempt to re-synchronize to
the data and assume that the bad stop bit is actually an early start bit.
However, it cannot be assumed that the next received byte will be correct
even if there is no Framing Error.
0: Framing error status is inactive.
1: Framing error status is active.
R
0
