SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 189
Version 1.1
16.6 I2S REGISTERS
Base Address: 0x4001 A000 (I2S0)
0x4001 4000 (I2S1)
16.6.1 I2S n Control register (I2Sn_CTRL) (n=0,1)
Address Offset: 0x00
Note: START bit shall be set at last.
Bit
Name
Description
Attribute
Reset
31
I2SEN
I2S enable bit
0: Disable
1: Enable
R/W
0
30:25
Reserved
R
0
24:20
CHLENGTH[4:0]
Bit number of single channel = CHLENGTH[4:0]+1.
0~6: Reserved
7: 8 bits
8: 9 bits
…
…
31: 32bits (Max)
R/W
0x1F
19
Reserved
R
0
18:16
RXFIFOTH[2:0]
RX FIFO Threshold level
0: RX FIFO threshold level = 0
1: RX FIFO threshold level = 1
…
…
n: RX FIFO threshold level = n
R/W
0x3
15
Reserved
R
0
14:12
TXFIFOTH[2:0]
TX FIFO Threshold level
0: TX FIFO threshold level = 0
1: TX FIFO threshold level = 1
…
…
n: TX FIFO threshold level = n
R/W
0x3
11:10
DL[1:0]
Data Length
00: 8 bit
01: 16 bits
10: 24 bits
11: 32 bits
R/W
0x1
9
CLRRXFIFO
Clear I2S RX FIFO
0: No effect.
1: Reset RX FIFO (RXFIFOLV bit becomes 0, RXFIFOEMPTY bit
becomes 1, Data in RX FIFO will be cleared). This bit returns “0”
automatically
W
0
8
CLRTXFIFO
Clear I2S TX FIFO
0: No effect.
1: Reset TX FIFO (TXFIFOLV bit becomes 0, TXFIFOEMPTY bit becomes
1, Data
in TX FIFO will be cleared). This bit returns “0” automatically
W
0
7
RXEN
Receiver enable bit
0: Disable
1: Enable
R/W
0
6
TXEN
Transmit enable bit
0: Disable
1: Enable
R/W
0
5:4
FORMAT[1:0]
I2S operation format.
00: Standard I2S format
01: Left-justified format
R/W
0
