SONIX SN32F280 Series, User Manual

Page: 244 / 268

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 244
Version 1.1
Bit Name Description Attribute Reset
31
PS2ENB
PS/2 internal 5kohm pull-up resistor control bit.
R/W 0
30:4 Reserved R 0
3
SDA
PS/2 SDA data buffer.
R/W 0
2 SCK
PS/2 SCK data buffer
R/W 0
1 SDAM
PS2/ SDA mode control bit.
R/W 0
0 SCKM
SCKM PS/2 SCK mode control bit.
R/W 0
20.9.15 USB Read/Write Address Register (USB_RWADDR)
Address Offset: 0x78
Reset value: 0x0000 0000
Bit Name Description Attribute Reset
31:9
Reserved R 0
8:2 RWADDR[6:0]
USB FIFO address to be read or written from/to USB FIFO.
R/W 0
1:0 Reserved R 0
20.9.16 USB Read/Write Data Register (USB_RWDATA)
Address Offset: 0x7C
Reset value: 0x0000 0000
Bit Name Description Attribute Reset
31:0 RWDATA[31:0]
Data to be read or written from/to USB FIFO.
R/W 0
20.9.17 USB Read/Write Status Register (USB_RWSTATUS)
Address Offset: 0x80
Reset value: 0x0000 0000
Bit Name Description Attribute Reset
31:2 Reserved R 0
1 R_STATUS
Read status of USB FIFO.
*If F/W is to read the data from USB FIFO, set this bit as ‘1 ’.
When hardware has completed the read action (RWDATA content
has been written by the new data read from USB FIFO with address
RWADDR.), this bit is automatically
cleared as ‘0’ by hardware.
R/W 0
0 W_STATUS
Write status of USB FIFO.
*If F/W is to write data
into USB FIFO, set this bit as ‘1 ’.
When hardware has completed the write action (RWDATA content
has been read as the new data, and the new data is written into USB
FIFO with address RWADDR.), this bit is
automatically cleared as ‘0’
by hardware.
R/W 0