SONIX SN32F280 Series, User Manual

Page: 133 / 268

SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 133
Version 1.1
Bit Name Description Attribute Reset
31:12 Reserved R 0
11 EM11
When EMC11
≠00b and MR11≠TC, this bit will drive the state of
CT16Bn_PWM11 output.
R/W 0
10 EM10
When EMC10
≠00b and MR10≠TC, this bit will drive the state of
CT16Bn_PWM10 output.
R/W 0
9 EM9
When EMC9
≠00b and MR9≠TC, this bit will drive the state of
CT16Bn_PWM9 output.
R/W 0
8 EM8
When EMC8
≠00b and MR8≠TC, this bit will drive the state of
CT16Bn_PWM8 output.
R/W 0
7 EM7
When EMC7
≠00b and MR7≠TC, this bit will drive the state of
CT16Bn_PWM7 output.
R/W 0
6 EM6
When EMC6
≠00b and MR6≠TC, this bit will drive the state of
CT16Bn_PWM6 output.
R/W 0
5 EM5
When EMC5
≠00b and MR5≠TC, this bit will drive the state of
CT16Bn_PWM5 output.
R/W 0
4 EM4
When EMC4
≠00b and MR4≠TC, this bit will drive the state of
CT16Bn_PWM4 output.
R/W 0
3 EM3
When EMC3
≠00b and MR3≠TC, this bit will drive the state of
CT16Bn_PWM3 output.
R/W 0
2 EM2
When EMC2
≠00b and MR2≠TC, this bit will drive the state of
CT16Bn_PWM2 output.
R/W 0
1 EM1
When EMC1
≠00b and MR1≠TC, this bit will drive the state of
CT16Bn_PWM1 output.
R/W 0
0 EM0
When EMC0
≠00b and MR0≠TC, this bit will drive the state of
CT16Bn_PWM0 output.
R/W 0
10.8.22 CT16Bn External Match Control register (CT16Bn_EMC) (n=1)
Address Offset: 0x90
The External Match Control register provides control of CT16B1_PWM[11:0]. If the match outputs are configured as
PWM output, the function of the external match registers is determined by the
PWM rules .