SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 225
Version 1.1
0: EBI_ARDY is inactive/busy
1: EBI_ARDY is active/ready
3:1
Reserved
R
0
0
EBIBUSY
EBI BUSY
0: EBI is idle
1: EBI is busy
R
0
18.7.4 EBI Address Timing register n (EBI_TADDRn) n=0~3
Address offset: 0x10, 0x14, 0x18, 0x1C
ADDRSETUP[3:0] is the number of cycles the EBI_AD bus is driven before EBI_ALE is asserted.
ADDRHOLD[3:0] is the number of cycles the EBI_AD bus is held after EBI_ALE is asserted.
Bit
Name
Description
Attribute
Reset
31:12
Reserved
R
0
11:8
ADDRHOLD[3:0]
Counts for Address Hold Time
Address Hold Time = ADDRHOLD[3:0] * EBI_PCLK
R/W
0xF
7:4
Reserved
R
0
3:0
ADDRSETUP[3:0]
Counts for Address Setup Time
0: Address Hold Time = 1 * EBI_PCLK
N: Address Hold Time = N * EBI_PCLK
R/W
0xF
18.7.5 EBI Read Timing register n (EBI_TREADn) n=0~3
Address offset: 0x20, 0x24, 0x28, 0x2C
RDSETUP[3:0] is the number of cycles for the address setup before EBI_OE is asserted.
RDSTRB [5:0] is the number of cycles the EBI_OE is held active, after the specified number of cycles, the data is read.
RDHOLD[3:0] is the number of cycles that the EBI_CSn is held active after EBI_OE is de-asserted. This interval is used
for bus turnaround.
Bit
Name
Description
Attribute
Reset
31:20
Reserved
R
0
19:16
RDHOLD[3:0]
Counts for Read Hold Time
Read Hold Time = RDHOLD[3:0] * EBI_PCLK
R/W
0xF
15:14
Reserved
R
0
13:8
RDSTRB[5:0]
Counts for Read Strobe Time
0: Read Strobe Time = 1 * EBI_PCLK
N: Read Strobe Time = N * EBI_PCLK
R/W
0x3F
7:4
Reserved
R
0
3:0
RDSETUP[3:0]
Counts for Read Setup Time
Read Setup Time = RDSETUP[3:0] * EBI_PCLK
R/W
0xF
18.7.6 EBI Write Timing register n (EBI_TWRITEn) n=0~3
Address offset: 0x30, 0x34, 0x38, 0x3C
WESETUP[3:0] is the number of cycles for the address setup before EBI_WE is asserted.
WESTRB [5:0] is the number of cycles the EBI_WE is held active.
WEHOLD[3:0] is the number of cycles that the EBI_CSn is held active after EBI_WE is de-asserted.
