SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 219
Version 1.1
18.5.7 EBI Bank Access
The EBI is split into 4 different address regions and each owns an individual CSn line. When accessing one of the
memory regions, the corresponding CSn line is asserted. Up to 4 separate devices can share the EBI lines and is
identified by the CSn line. Each bank can individually be enabled or disabled in the EBI_CTRL register. And each bank
can individually define the external device behavior, including the data width, the timing definitions, and the pin polarities.
The data space of each bank can be accessed up to 64MB, and the EBI regions address starts at 0x60000000 in the
memory map. When running code via EBI regions starting at this address, the Cortex-M0 uses the System bus interface
to fetch instructions.
18.5.8 EBI Ready
Some external devices are able to indicate that they have not finished the write or read operation by asserting the wait
signal. The EBI_ARDY input signal is used to extend the read or write cycles for slow external devices when it is
enabled ARDY
N
EN bit = 1 in the EBI_CTRL register. EBI_ARDY can be configured by the polarity of this signal with the
ARDYPOL bit in the EBIPR register. If the ARDYPOL bit is set to active low, then the read or write cycle is extended
while the EBI_ARDY line is kept high. It also provides a timeout check to prevent a system lock up condition in case
where the external device does not de-assert the EBI_ARDY signal. It will generate a bus asynchronous ready time-out
interrupt if EBI_ARDY is not deasserted within the timeout period. This timeout period has a default value of 32 HLCK
clock cycles. Its functionality can be disabled by setting the ARDYTDIS bit in the EBI_CTRL register. Note that each
memory bank can individually set its wait behavior definition.
18.6 8080 MODE DMA-CONTROLLED TFT-LCD
Direct memory access (DMA) is used in order to provide high-speed data transfer between external SPI-flash and
TFT-LCD. Data can be moved from SPI FIFOs to TFT-LCD by DMA without any CPU actions. This keeps CPU
resources free for other operations.
The 8080 MODE DMA only supports RGB565 (65536 colors) format, and the data length of SPIn is 8 bits. Set the total
bytes of the SPI FLASH which DMA transferred in
