SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 113
Version 1.1
10.5 TIMER OPERATION
10.5.1 Edge-aligned Up-counting Mode
The following figure shows a timer configured to reset the count (TC) and generate an interrupt on match in
Edge-aligned up-counting mode. The
end of the timer cycle where the match occurs, the timer count is reset. This gives a full length cycle to the match value.
The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value.
PCLK
CT16Bn_PC
CT16Bn_TC
TC Reset
Interrupt
2
0
1
2
0
1
2
0
4
5
6
0
The following figure shows a timer configured to stop and generate an interrupt on match in Edge-aligned up-counting
mode. The
register is set to 6. In the next clock after the timer
reaches the match value, the CEN bit in
register is cleared, and the interrupt indicating that a match
occurred is generated.
PCLK
CT16Bn_PC
CT16Bn_TC
CEN bit
Interrupt
2
0
1
2
0
4
5
6
1
0
