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SN32F280 Series

32-Bit Cortex-M0 Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 217

Version 1.1

- NOIDLE = 0:

A[N:0]

ADDR0

RDSETUP

(0, 1, 2, …)

RDSTRB

(1, 2, 3, …)

AD[15:0]

CSn

OE

RDHOLD

(0, 1, 2, …)

IDLE

RDSETUP

(0, 1, 2, …)

RDSTRB

(1, 2, 3, …)

RDHOLD

(0, 1, 2, …)

IDLE

ADDR1

DATA0

DATA1

- NOIDLE = 1:

A[N:0]

ADDR0

RDSETUP

(0, 1, 2, …)

RDSTRB

(1, 2, 3, …)

AD[15:0]

CSn

OE

RDHOLD

(0, 1, 2, …)

RDSETUP

(0, 1, 2, …)

RDSTRB

(1, 2, 3, …)

RDHOLD

(0, 1, 2, …)

IDLE

ADDR1

DATA0

DATA1

18.5.6 AHB Transaction Width Conversion

The mapping of AHB transactions to an external device depends on the data width of the external device and whether
the byte lanes of the external device are supported or not. The EBI will automatically translate the different AHB
transaction width to external device transactions which matches the external bus capabilities of the device.



If the AHB master (CPU) transaction width is larger than the external bus transaction width. The EBI will split and
translate the AHB transaction into consecutive multiple external transactions which have consecutively
incrementing the address and start with the least significant data from AHB transaction.



If the AHB master (CPU) transaction width is smaller than the external bus transaction width. The EBI behaviour
depends on whether the byte lanes are available or not. Reads either use byte lanes to select the required data
when it is available, or read according to the full data bus width of the external device and ignore the superfluous
data when a byte lane is not available. Writes either use a byte lane to select the required data when it is available,

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Summary of Contents for SN32F280 Series

Page 1: ...us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product...

Page 2: ...D Page 2 Version 1 1 AMENDENT HISTORY Version Date Description 1 0 2020 03 25 First version released 1 1 2020 06 01 1 Fix typing errors 2 Update the CMP and OPA block diagram 3 Add I2C0PRE and I2C1PRE...

Page 3: ...2 System Tick Timer Reload value register SYSTICK_LOAD 40 2 2 3 3 System Tick Timer Current Value register SYSTICK_VAL 41 2 2 3 4 System Tick Timer Calibration Value register SYSTICK_CALIB 41 2 3 NES...

Page 4: ...CK SOURCE 57 3 2 3 1 External High speed EHS Clock 57 3 2 3 2 CRYSTAL CERAMIC 57 3 2 3 3 External Low speed ELS Clock 58 3 2 3 4 CRYSTAL 58 3 2 3 5 Bypass Mode 59 3 2 4 SYSTEM CLOCK SYSCLK SELECTION 5...

Page 5: ...76 5 5 5 GENERAL PURPOSE I O PORT GPIO 77 5 1 OVERVIEW 77 5 2 GPIO MODE 77 5 3 GPIO REGISTERS 78 5 3 1 GPIO Port n Data register GPIOn_DATA n 0 1 2 3 78 5 3 2 GPIO Port n Mode register GPIOn_MODE n 0...

Page 6: ...GITAL CONVERTOR ADC 92 7 1 OVERVIEW 92 7 2 ADC CONVERTING TIME 93 7 3 ADC CONTROL NOTICE 94 7 3 1 ADC SIGNAL 94 7 3 2 ADC PROGRAM 94 7 3 3 ADC PIN CONFIGURATION 94 7 4 ADC CIRCUIT 95 7 5 ADC REGISTERS...

Page 7: ...ERS 120 10 8 1 CT16Bn Timer Control register CT16Bn_TMRCTRL n 0 2 120 10 8 2 CT16Bn Timer Control register CT16Bn_TMRCTRL n 1 3 4 121 10 8 3 CT16Bn Timer Control register CT16Bn_TMRCTRL n 5 121 10 8 4...

Page 8: ...atus register CT16Bn_RIS n 3 4 141 10 8 30 CT16Bn Timer Raw Interrupt Status register CT16Bn_RIS n 1 141 10 8 31 CT16Bn Timer Interrupt Clear register CT16Bn_IC n 0 2 5 142 10 8 32 CT16Bn Timer Interr...

Page 9: ...egister 0 SPIn_CTRL0 n 0 1 157 13 6 2 SPI n Control register 1 SPIn_CTRL1 n 0 1 158 13 6 3 SPI n Clock Divider register SPIn_CLKDIV n 0 1 158 13 6 4 SPI n Status register SPIn_STAT n 0 1 158 13 6 5 SP...

Page 10: ...TRANSMITTER UART 171 15 1 OVERVIEW 171 15 2 FEATURES 171 15 3 PIN DESCRIPTION 171 15 4 BLOCK DIAGRAM 172 15 5 BAUD RATE CALCULATION 173 15 6 AUTO BAUD FLOW 174 15 6 1 AUTO BAUD 174 15 6 2 AUTO BAUD M...

Page 11: ...n 0 1 191 16 6 6 I2S n Interrupt Clear register I2S_IC n 0 1 192 16 6 7 I2S n RXFIFO register I2S_RXFIFO n 0 1 192 16 6 8 I2S n TXFIFO register I2S_TXFIFO n 0 1 192 1 1 17 7 7 4X40 6X38 7X37 8X36 LCD...

Page 12: ...t Data Mode AND16ALE 215 18 5 4 Write Buffer and EBI Status 216 18 5 5 Bus Turn around and Idle Cycles 216 18 5 6 AHB Transaction Width Conversion 217 18 5 7 EBI Bank Access 219 18 5 8 EBI Ready 219 1...

Page 13: ..._INSTSC 239 20 9 4 USB Device Address Register USB_ADDR 240 20 9 5 USB Configuration Register USB_CFG 240 20 9 6 USB Signal Control Register USB_SGCTL 241 20 9 7 USB Endpoint 0 Control Register USB_EP...

Page 14: ...RL 250 21 11 2 Flash Status register FLASH_STATUS 250 21 11 3 Flash Control register FLASH_CTRL 250 21 11 4 Flash Data register FLASH_DATA 251 21 11 5 Flash Address register FLASH_ADDR 251 21 11 6 Fla...

Page 15: ...1 1 2 2 25 5 5 FLASH ROM PROGRAMMING PIN 261 2 2 26 6 6 PACKAGE INFORMATION 262 26 1 LQFP 80 PIN 262 26 2 LQFP 64 PIN 263 26 3 LQFP 48 PIN 264 2 2 27 7 7 MARKING DEFINITION 265 27 1 INTRODUCTION 265...

Page 16: ...er 3 external negative inputs Programmable Watchdog Timer WDT 3 external positive inputs Programmable watchdog frequency with watchdog clock source and divider 2 OPA Internal reference voltage source...

Page 17: ...ve Touch Keys Support R type Up to 8 com 3 3V Regulator output 4x40 or 6x38 or 7x37 or 8x36 dots Driving current 60mA 1 3 bias voltage Power for USB D internal pull up resistor Adjustable VLCD Voltage...

Page 18: ...ROM BOOT LOADER 4KB AIN0 AIN15 PMU COM0 COM7 SEG0 SEG39 LCD WDT 16 bit TIMER 5 with PWM ADC CT16B4_PWM 1 0 CT16B4_PWM 1 0 N CT16B4_CAP0 16 bit TIMER 4 with PWM CT16B3_PWM 1 0 CT16B3_PWM 1 0 N CT16B3_C...

Page 19: ...1 2 3 UARTn register block UARTn clock source AHB clock for SRAM SRAM block AHB clock for FLASH FLASH block Max 16MHz CLKOUT Prescaler 1 2 4 128 WDTCLKEN HCLK IHRC ILRC 32 768KHz RTC_PCLK RTC registe...

Page 20: ...11 12 49 P0 12 SEG27 CM2N0 SEG20 AIN12 P2 12 13 48 P0 13 SEG26 16B4_CAP0 CM2P0 SEG21 AIN13 P2 13 14 47 P0 14 SEG25 AD8 16B3_CAP0 CM2P2 P0 4 15 46 P0 15 SEG24 AD9 CM2N2 P0 5 16 45 P0 16 16B5_CAP0 CT0 C...

Page 21: ...CM2N2 P0 5 13 36 P1 15 SEG15 AD7 CT0 CM0N2 AIN0 P2 0 14 35 P1 14 SEG14 CT15 AD6 CT1 CM0P0 SEG0 AIN1 P2 1 15 34 P1 13 SEG13 CT14 AD5 CT2 CM1N2 SEG1 AIN2 P2 2 16 33 P1 12 SEG12 CT13 AD4 17 18 19 20 21 2...

Page 22: ...P0 SEG0 AIN1 P2 1 11 26 P1 13 SEG13 CT14 AD5 CT2 CM1N2 SEG1 AIN2 P2 2 12 25 P1 12 SEG12 CT13 AD4 13 14 15 16 17 18 19 20 21 22 23 24 CT3 CM1P0 SEG2 AIN3 P2 3 AD10 CT4 CM1N0 AIN4 P2 4 AD11 CT5 CM1N1 AI...

Page 23: ...1_PWM4 B3_CAP0 CM2P2 AD8 P0 5 B1_PWM5 CM2N2 AD9 P0 6 SCL0 B1_PWM6 P0 7 SDA0 B1_PWM7 CM1P2 P0 8 B1_PWM8 B3_PWM1N B4_PWM0N A24 P0 9 B1_PWM9 B2_CAP0 B4_PWM0 A25 P0 10 UTXD0 SCL0 B1_PWM10 B3_PWM0N B4_PWM0...

Page 24: ...B0_PWM0N B1_PWM5 B3_PWM1N B4_PWM1N SEG13 CT14 AD5 P1 14 MISO1 SDA1 MCLK1 B0_PWM1N B1_PWM6 B3_PWM0 SEG14 CT15 AD6 P1 15 MOSI1 DOUT1 B0_PWM2N B1_PWM7 B3_PWM0N B3_PWM1 SEG15 CSCAP AD7 P1 16 UTXD1 SEG34...

Page 25: ...IN12 CM2N0 SEG20 P2 13 MOSI1 DOUT1 AIN13 CM2P0 SEG21 P2 14 UTXD2 B0_PWM3 AIN14 CM0P1 SEG22 P2 15 URXD2 B0_PWM3N AIN15 CM0P2 SEG23 CT8 P3 0 SCK0 MCLK0 B0_PWM0 COM0 A0 CLKOUT P3 1 UTXD0 MISO0 BCLK0 B0_P...

Page 26: ...D0 Address Data 0 for EBI P0 1 SEG10 AD1 I O P0 1 General purpose digital input output pin AD1 Address Data 1 for EBI O SEG10 Segment output 10 for LCD driver P0 2 SEG11 AD2 I O P0 2 General purpose d...

Page 27: ...eral purpose digital input output pin O SEG26 Segment output 26 for LCD driver I CT16B4_CAP0 Capture input 0 for CT16B4 P0 14 SEG25 I O P0 14 General purpose digital input output pin O SEG25 Segment o...

Page 28: ...ime P1 4 SEG16 OP0P A22 I O P1 4 General purpose digital input output pin I OP0P Positive input pin of OPA 0 O SEG16 Segment 16 output for LCD A22 Address 22 for EBI P1 5 COM3 OP0O A23 I O P1 5 Genera...

Page 29: ...SEG13 Segment 13 output for LCD P1 14 SEG14 AD6 I O P1 14 General purpose digital input output pin AD6 Address Data 6 for EBI O SEG14 Segment 14 output for LCD P1 15 SEG15 AD7 I O P1 15 General purpo...

Page 30: ...tive input pin 0 of comparator 1 O SEG2 Segment 2 output for LCD P2 4 AIN4 CM1N0 AD10 I O P2 4 General purpose digital input output pin AD10 Address Data 10 for EBI I AIN4 ADC channel input 4 CM1N0 Ne...

Page 31: ...19 CM0N1 I O P2 11 General purpose digital input output pin I AIN11 ADC channel input 11 CM0N1 Negative input pin 1 of comparator 0 O SEG19 Segment 19 output for LCD P2 12 AIN12 SEG20 CM2N0 I O P2 12...

Page 32: ...urpose digital input output pin I SWCLK Serial wire clock P3 7 RESET I O P3 7 General purpose digital input output pin I RESET External Reset input P3 8 CT16B1_CAP0 CS0 I O P3 8 General purpose digita...

Page 33: ...r EBI P3 16 CS2 I O P3 16 General purpose digital input output pin O CS2 Chip Select 2 for EBI P3 17 CS3 I O P3 17 General purpose digital input output pin O CS3 Chip Select 3 for EBI P3 18 ARDY I O P...

Page 34: ...RPU Output Latch Pin GPIOn_CFG I O Input Bus Output Bus GPIOPn_MODE Specific Input Bus Specific Input Function Control Bit Some specific functions switch I O direction directly not through GPIOn_MODE...

Page 35: ...Specific Output Function Control Bit Some specific functions switch I O direction directly not through GPIOn_MODE register Analog IP Input Terminal Bi direction I O Pin Shared with Specific Analog Out...

Page 36: ...V P0 16 I O V P0 17 I O V P0 18 I O V P0 19 I O P1 0 I O V V V P1 1 I O V V V V P1 2 I O V V V V P1 3 I O V V V P1 4 I O V V V V P1 5 I O V V V V P1 6 I O V V P1 7 I O V V P1 8 I O V V V V P1 9 I O V...

Page 37: ...ro Controller SONiX TECHNOLOGY CO LTD Page 37 Version 1 1 P3 6 I O V V P3 7 I O V P3 8 I O V P3 9 I O V P3 10 I O V V P3 11 I O V V P3 12 I O V V P3 13 I O V V P3 14 I O V V P3 15 I O V V P3 16 I O V...

Page 38: ...rved 0x4008 0000 0xE000 0000 0xE010 0000 0xE000 ED00 0xE000 F000 Reserved NVIC Debug Control 0xE000 E000 Reserved SPI 0 UART0 SYS0 SPI 1 UART 1 0x4006 0000 FMC Reserved CT16B0 CT16B1 CT16B2 CT16B3 RTC...

Page 39: ...fixed 10 ms time interval between interrupts The system tick timer is enabled through the SysTick control register The system tick timer clock is fixed to the frequency of the system clock The block...

Page 40: ...Reserved R 0 2 CLKSOURCE Selects the SysTick timer clock source 0 reference clock 1 system clock Fixed R 1 1 TICKINT System Tick interrupt enable 0 Disable the System Tick interrupt 1 Enable the Syste...

Page 41: ...W 0x7E7F35 2 2 3 4 System Tick Timer Calibration Value register SYSTICK_CALIB Address 0xE000 E01C Refer to Cortex M0 Spec Bit Name Description Attribute Reset 31 NOREF Indicates the reference clock to...

Page 42: ...r Non maskable interrupt 0x0000 0008 3 1 HardFault_Handler All class of fault 0x0000 000C 4 10 Reserved Reserved Reserved 11 Settable SVCCalll 0x0000 002C 12 13 Reserved Reserved Reserved 14 Settable...

Page 43: ...0x0000 00B0 45 Settable IRQ29 P2IRQ GPIO interrupt status of port 2 0x0000 00B4 46 Settable IRQ30 P1IRQ GPIO interrupt status of port 1 0x0000 00B8 47 Settable IRQ31 P0IRQ GPIO interrupt status of po...

Page 44: ...0 31 Interrupt Priority Register NVIC_IPRn n 0 7 Address 0xE000 E400 0x4 n Refer to Cortex M0 Spec The interrupt priority registers provide an 8 bit priority field for each interrupt and each register...

Page 45: ...ore can be reset by SW by setting the SYSRESREQ bit in the AIRC register in Cortex M0 spec Note To write to this register user must write 0x05FA to the VECTKEY field at the same time otherwise the pro...

Page 46: ...trol with SYS0_EXRSTCTRL 1 Disable default FW can control with SYS0_EXRSTCTRL R W 1 0 BLEN Boot loader enable 0 Disable 1 Enable default R W 1 2 6 UNIQUE NUMBER The unique number is a 8 byte unique de...

Page 47: ...ster LR It stores the return information for subroutines function calls and exceptions PC R15 The Program Counter PC It contains the current program address On reset the processor loads the PC with th...

Page 48: ...application users have to take care of the power on reset time for the master terminal requirement The reset timing diagram is as following VDD VSS VDD VSS Watchdog Normal Run Watchdog Stop System Nor...

Page 49: ...st structure to enhance the watchdog timer function Note Please refer to the WATCHDOG TIMER about watchdog timer detail information 3 1 3 BROWN OUT RESET 3 1 3 1 BROWN OUT DESCRIPTION The brown out re...

Page 50: ...level Different system executing rates have different system minimum operating voltage The electrical characteristic section shows the system voltage to executing rate relationship Vdd V System Rate F...

Page 51: ...urn normal mode If the system reset by watchdog and the power is still in dead band the system reset sequence won t be successful and the system stays in reset status until the power return to normal...

Page 52: ...hm C1 0 1uF R2 100 ohm This is the basic reset circuit and only includes R1 and C1 The RC circuit operation makes a slow rising signal into reset pin as power up The reset signal is slower than VDD po...

Page 53: ...T R1 33K ohm R3 40K ohm R2 10K ohm Vz Q1 E C B The Zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely Use Zener voltage to be the active le...

Page 54: ...system power consumption Note Under unstable power condition as brown out reset Zener diode reset circuit and Voltage bias reset circuit can protects system no any error occurrence as power dropping...

Page 55: ...scillator on chip PLL circuit The low speed clock is generated from on chip low speed RC oscillator circuit ILRC 16 KHz 3 2 1 INTERNAL RC CLOCK SOURCE 3 2 1 1 Internal High speed RC Oscillator IHRC Th...

Page 56: ...edback divider to generate the feedback clock The output signal of the phase frequency detector is also monitored by the lock detector to signal when the PLL has locked on to the input clock The PLL s...

Page 57: ...evices are driven by XIN XOUT pins For high normal low frequency the driving currents are different MCU VCC GND C 20pF XIN XOUT VDD VSS C 20pF CRYSTAL Note Connect the Crystal Ceramic and C as near as...

Page 58: ...hed on and off using the EHSEN bit in Analog Block Control register SYS0_ANBCTRL 3 2 3 3 External Low speed ELS Clock The low speed oscillator can use 32768 crystal oscillator circuit 3 2 3 4 CRYSTAL...

Page 59: ...4 SYSTEM CLOCK SYSCLK SELECTION After a system reset the IHRC is selected as system clock When a clock source is used directly or through the PLL as system clock it is not possible to stop it A switc...

Page 60: ...EHS X TAL R W 0 3 Reserved R 0 2 ELSEN External low speed oscillator enable 0 Disable External 32 768 KHz oscillator 1 Enable External 32 768 KHz oscillator R W 0 1 Reserved R 0 0 IHRCEN Internal high...

Page 61: ...FCLKOUT FVCO P FCLKIN MHz MSEL 2 0 M FVCO MHz FCLKIN M 96 MHz PSEL P FCLKOUT MHz FVCO P 12 010b 8 96 0 2 48 16 001b 6 96 0 2 48 3 3 3 Clock Source Status register SYS0_CSST Address Offset 0x08 Bit Nam...

Page 62: ...10 Bit Name Description Attribute Reset 31 4 Reserved R 0 3 DIV1P5 SYSCLK prescaler 0 SYSCLK SYSCLK clock source 1 1 SYSCLK SYSCLK clock source 1 5 R W 0 2 0 AHBPRE 2 0 AHB clock source prescaler 000...

Page 63: ...nterrupt to the NVIC or LVD reset Bit Name Description Attribute Reset 31 16 Reserved R 0 15 LVDEN LVD enable 0 Disable 1 Enable R W 0 14 LVDRSTEN LVD Reset enable 0 Disable 1 Enable R W 0 13 7 Reserv...

Page 64: ...rrupt vector table is mapping to Boot ROM User ROM or SRAM 0x0000 0000 0x0001 0000 0x0002 0000 User ROM 1 User ROM 2 Bit Name Description Attribute Reset 31 16 IVTMKEY 15 0 IVTM register key Read as 0...

Page 65: ...This register decides the HW anti EFT ability Bit Name Description Attribute Reset 31 3 Reserved R 0 2 0 AEFT 2 0 HW anti EFT ability 000 No 010 Low 011 Medium 100 Strong R W 000 3 3 14 IHRC Frequency...

Page 66: ...31 Reserved R 0 30 28 CLKOUTSEL 2 0 Clock output source 000 Disable 001 ILRC clock 010 ELS clock 100 HCLK 101 IHRC clock 110 EHS clock 111 PLL clock output Other Disable R W 0 27 CRCCLKEN Enables clo...

Page 67: ...CT16B4 0 Disable 1 Enable R W 0 8 CT16B3CLKEN Enables clock for CT16B3 0 Disable 1 Enable R W 0 7 CT16B2CLKEN Enables clock for CT16B2 0 Disable 1 Enable R W 0 6 CT16B1CLKEN Enables clock for CT16B1 0...

Page 68: ...urce 64 111 Clock out source 128 R W 0 27 Reserved R 0 26 24 I2C1PRE 2 0 I2C1 clock source prescaler 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved W 0 23 Reserved R 0 22 20 WD...

Page 69: ...t CRC R W 0 25 I2S1RST I2S1 reset 0 No effect 1 Reset I2S1 R W 0 24 WDTRST WDT reset 0 No effect 1 Reset WDT R W 0 23 RTCRST RTC reset 0 No effect 1 Reset RTC R W 0 22 I2S0RST I2S0 reset 0 No effect 1...

Page 70: ...T32B0 reset 0 No effect 1 Reset CT32B0 R W 0 7 CT16B2RST CT16B2 reset 0 No effect 1 Reset CT16B2 R W 0 6 CT16B1RST CT16B1 reset 0 No effect 1 Reset CT16B1 R W 0 5 CT16B0RST CT16B0 reset 0 No effect 1...

Page 71: ...rolled as needed by changing clock sources re configuring PLL values and or altering the system clock divider value This allows a trade off of power versus processing speed based on application requir...

Page 72: ...ed clock source ELS X TAL ILRC if used Note User SHALL decide to power down low speed clock source ELS X TAL ILRC oscillator or not if RTC or LCD is enabled The processor state and registers periphera...

Page 73: ...illator clocks as the wakeup time to stable the oscillator circuit After the wakeup time the system goes into the normal mode Note Wakeup from Sleep mode spends NO wakeup time if the clock doesn t sto...

Page 74: ...p sleep mode Sleep mode Wake up condition Interrupt Wake up condition GPIO Wakeup RTC interrupt LCD interrupt CT16B5 interrupt Reset condition One of reset trigger sources actives Reset condition One...

Page 75: ...able if used as clock source of LCD RTC CT16B5 PLL By PLLEN Disable Cortex M0 Running Stop Stop Flash ROM Enable Disable Disable RAM Enable Maintain Maintain USB By USBEN Disable ADC By ADENB Disable...

Page 76: ...power down modes respectively Note 1 The PMU_CTRL register retains data through the Deep power down mode when power is still applied to the VDD pin and will be reset only when all power has been compl...

Page 77: ...be configured on single falling or rising edges and on both edges The I O configuration registers control the electrical characteristics of the pads Internal pull up pull down resistor Most of the I...

Page 78: ...0 Select pin x as input or output x 0 to 19 0 Pn x is configured as input 1 Pn x is configured as output R W 0 5 3 3 GPIO Port n Configuration register GPIOn_CFG n 0 1 2 3 Address offset 0x08 Reset va...

Page 79: ...r enabled Schmitt trigger disabled Data register keep low R W 10b 17 16 CFG8 1 0 Configuration of Pn 8 00 Pull up resistor enabled 01 Reserved 10 Inactive no pull down up resistor enabled Schmitt trig...

Page 80: ...e x 0 to 19 0 Interrupt on Pn x is configured as edge sensitive 1 Interrupt on Pn x is configured as event sensitive R W 0 5 3 5 GPIO Port n Interrupt Both edge Sense register GPIOn_IBS n 0 1 2 3 Addr...

Page 81: ...nterrupt Clear register GPIOn_IC n 0 1 2 3 Address offset 0x20 Bit Name Description Attribute Reset 31 20 Reserved R 0 19 0 IC 19 0 Select the interrupt flag on pin x to be cleared x 0 to 19 0 No effe...

Page 82: ...ata register keep low R W 10b 5 4 CFG18 1 0 Configuration of Pn 18 00 Pull up resistor enabled 01 Reserved 10 Inactive no pull down up resistor enabled Schmitt trigger enabled 11 Inactive no pull down...

Page 83: ...n Name PA0 PA1 PA2 PA3 UART0 URXD0 P0 11 P2 0 P3 2 UTXD0 P0 10 P2 1 P3 1 UART1 URXD1 P1 8 P2 3 P1 17 UTXD1 P1 9 P2 2 P1 16 P3 6 UART2 URXD2 P0 2 P1 3 P2 15 P1 6 UTXD2 P0 1 P1 4 P2 14 P1 7 UART3 URXD3...

Page 84: ...P0 0 P1 16 P0 2 P2 15 CT16B1 PWM0 P0 0 P1 8 PWM1 P0 1 P1 9 PWM2 P0 2 P1 10 PWM3 P0 3 P1 11 PWM4 P0 4 P1 12 PWM5 P0 5 P1 13 PWM6 P0 6 P1 14 PWM7 P0 7 P1 15 PWM8 P0 8 P2 0 PWM9 P0 9 P2 4 PWM10 P0 10 P2...

Page 85: ...P2 14 R W 0 11 10 PWM2N 1 0 Pin to be assigned as CT16B0_PWM2N 00 P1 15 01 P2 6 10 P2 9 11 P0 1 R W 0 9 8 PWM2 1 0 Pin to be assigned as CT16B0_PWM2 00 P2 7 01 P3 2 10 P0 0 11 P2 8 R W 0 7 6 PWM1N 1...

Page 86: ...be assigned as CT16B1_PWM04 1 P1 12 0 P0 4 R W 0 3 PWM03 Pin to be assigned as CT16B1_PWM03 1 P1 11 0 P0 3 R W 0 2 PWM02 Pin to be assigned as CT16B1_PWM02 1 P1 10 0 P0 2 R W 0 1 PWM01 Pin to be assi...

Page 87: ...r PFPA_I2C Address offset 0x0C Bit Name Description Attribute Reset 31 8 Reserved R 0 7 6 SCL1 1 0 Pin to be assigned as SCL1 00 P1 10 01 P1 13 10 P0 1 11 P1 8 R W 0 5 4 SDA1 1 0 Pin to be assigned as...

Page 88: ...e assigned as MOSI0 00 P0 3 01 P2 7 10 P1 2 11 P3 2 R W 0 1 0 MISO0 1 0 Pin to be assigned as MISO0 00 P0 2 01 P2 6 10 P1 1 11 P3 1 R W 0 6 4 6 PFPA for I2S register PFPA_I2S Address offset 0x14 Bit N...

Page 89: ...0 01 P2 6 10 P1 1 11 Reserved R W 0 6 4 7 PFPA for CT16B2 register PFPA_CT16B2 Address offset 0x18 Bit Name Description Attribute Reset 31 8 Reserved R 0 7 6 PWM3 1 0 Pin to be assigned as CT16B2_PWM...

Page 90: ...ttribute Reset 31 8 Reserved R 0 7 6 PWM1N 1 0 Pin to be assigned as CT16B4_PWM1N 00 P0 10 01 P1 3 10 P2 4 11 P1 13 R W 0 5 4 PWM1 1 0 Pin to be assigned as CT16B4_PWM1 00 P2 6 01 P1 4 10 P2 5 11 P1 1...

Page 91: ...Controller SONiX TECHNOLOGY CO LTD Page 91 Version 1 1 11 P3 18 3 2 PWM1 1 0 Pin to be assigned as CT16B5_PWM1 00 P2 7 01 P0 14 10 P1 2 11 P3 17 R W 0 1 0 PWM0 1 0 Pin to be assigned as CT16B5_PWM0 0...

Page 92: ...the ADC pins returns to GPIO last status including pull up pull down resistor Use CHS 4 0 to select AIN pin and GCHS enables global ADC channel the analog signal inputs to ADC engine The ADC resolutio...

Page 93: ...n rate the ADC result would be error So to select a correct ADC clock rate and ADC resolution to decide a right ADC converting rate is very important 12 bit ADC conversion time 1 ADC clock 4 16 sec AD...

Page 94: ...not ADS setting or the ADC converting result would be error Normally the ADENB is set one time when the system under normal run condition and do the delay time only one time Step 2 If the ADC high ref...

Page 95: ...ram 7 4 ADC CIRCUIT VCC GND 0 1uF Analog Signal Input 47uF 0 1uF External High Reference Voltage Main Power Trunk AINn P2 n VSS AVREFH MCU A B C The analog signal is inputted to ADC input pin AINn P2...

Page 96: ...Bit Name Description Attribute Reset 31 17 Reserved R 0 16 14 VHS 2 0 Internal reference voltage level selection 000 Internal 2 0V as ADC internal reference high voltage 001 Internal 3 0V as ADC inter...

Page 97: ...0 0 0 0 0 0 0 0 0 0 1 4096 VREFH 0 0 0 0 0 0 0 0 0 0 0 1 4094 4096 VREFH 1 1 1 1 1 1 1 1 1 1 1 0 4095 4096 VREFH 1 1 1 1 1 1 1 1 1 1 1 1 For different applications users maybe need more than 8 bit res...

Page 98: ...t x is one completion of a conversion on AIN x will generate an interrupt R W 0 7 5 4 ADC Raw Interrupt Status register ADC_RIS Address offset 0x10 Bit Name Description Attribute Reset 31 19 Reserved...

Page 99: ...upt service executed when CMnIE bit is set CMnO CMn G CMnOUT CMnIF _ Vdd Vss CMnN1 CMnEN CMnOEN CMnEN CMnMODE CMnI E CMnIRQ Comparator 0 Output De bounce time No 21 27 T CMPn_PCLK CMnDB 3 0 CMnN2 CMnN...

Page 100: ...S 4 0 CMPIREFEN 1 32 2 32 31 32 32 32 VOPAIREF CMPIREFEN The main purposes of comparator are as following Normal comparator function General comparator mode compares the two tensions of positive input...

Page 101: ...CM1N1 or CM1N2 pin When CM1NS 1 0 11b the comparator negative positive voltage is from internal reference and CM1N0 1 2 pins are GPIO function When CM1PS 1 0 01b 11b the comparator positive input is...

Page 102: ...OUT changes from low to high or falling edge CMnOUT changes from high to low controlled by CMnG bit When CMnG 0 the comparator n interrupt trigger direction is falling edge When CMnG 1 the comparator...

Page 103: ...nt status The de bounce time is controlled by CM0DB 2 0 bits that means the comparator minimum response time is 2 CMP_PCLK 4 CMP_PCLK 8 CMP_PCLK 128 CMP_PCLK or no de bounce The de bounce time depends...

Page 104: ...is comparator positive input pin and isolate GPIO function 11 CM1P2 is comparator positive input pin and isolate GPIO function R W 01b 16 CM1EN CMP1 enable bit 0 Disable CM1P0 1 2 CM1N0 1 2 CM1O are G...

Page 105: ...s comparator negative input pin and isolate GPIO function 11 VIREF2 CM2N0 CM2N1 CM2N2 pins are GPIO mode R W 00b 2 1 CM2PS 1 0 CMP2 positive input pin selection bit 00 Reserved CM2P0 CM2P1 CM2P2 pins...

Page 106: ...1 Enable R W 0 8 4 6 CMP Raw Interrupt Status register CMP_RIS Address offset 0x14 This register indicates the status for comparator raw interrupts A CMP0 1 2 interrupt is sent to the interrupt contr...

Page 107: ...be cleared 0 No effect 1 Clear CM0IF bit W 0 8 4 8 CMP Output Debounce register CMP_DB Address offset 0x1C Bit Name Description Attribute Reset 31 11 Reserved R 0 10 8 CM2DB 2 0 Count for CMP2 output...

Page 108: ...N18 for voltage measurement The internal reference regulator of the comparator is also shared with OPA Internal Reference Regulator 3V 2V 1 5V VDD VIREF CMPIREF VOPAIREF CMPIREFEN CMnEN OPnO _ Vdd Vss...

Page 109: ...OGY CO LTD Page 109 Version 1 1 OPA0 0 All shared pins are GPIO mode 1 OP0P if OP0PS 1 VOPAIREF if OP0PS 0 OP0N if OP0NS 1 VOPAIREF if OP0NS 0 OP0O OPA1 0 All shared pins are GPIO mode 1 OP1P if OP1PS...

Page 110: ...pin is GPIO mode 1 OP1P OP1P is OPA1 positive input pin and isolate GPIO function R W 0 10 9 Reserved R 0 8 OP1EN OP Amp 1 enable bit 0 Disable OP1O OP1P OP1N pins are GPIO mode 1 Enable OP1O is OP A...

Page 111: ...PWM0 1 2 3 PCLK max 96MHz max 96MHz max 96MHz max 96MHz max 96MHz max 96MHz 10 2 FEATURES Six 16 bit counter timers with a programmable 8 bit prescaler Counter or timer operation Six 16 bit capture ch...

Page 112: ...ut 0 Depends on GPIOn_CFG CT16Bn_PWMx O Output channel x of Match PWM output CT16Bn_PWMxN O Inverse Output channel of Match PWMx output 10 4 BLOCK DIAGRAM CT16Bn_PWMx STOP MRx MRxIF MRxIE PCLK CEN PC...

Page 113: ...full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value PCLK CT16Bn_PC CT16Bn_TC TC Reset Interrupt 2...

Page 114: ...g mode The CT16Bn_PRE register is set to 0 and the CT16Bn_MR3 register is set to 54 After TC reaches 0 the timer count is reset and loaded from the value of CT16Bn_MR3 PCLK CT16Bn_TC 4 3 2 1 0 54 53 5...

Page 115: ...e PWM output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length 5 If a ma...

Page 116: ...al to zero 2 Each PWM output will go LOW when its match value is reached If no match occurs the PWM output remains continuously HIGH 3 If a match value larger than the PWM cycle length is written to t...

Page 117: ...n the match outputs are selected to perform as PWM outputs the timer reset MRnRST and timer stop MRnSTOP bits in CT16Bn_MCTRL register must be set to zero except for the match register setting the PWM...

Page 118: ...tput pin which outputs the same PWMm signal with dead band period The dead band period is symmetrical at left right terminal of PWM high pulse width and the PWM dead band period is controlled by CT16B...

Page 119: ...Band Dead Band Dead Band Note If the bead band period is longer than PWM duty the PWM1N is no output Note When the dead band function is enabled in Center aligned mode and MR9RST 1 CT16Bn_PWMxN will...

Page 120: ...3 4 5 0x84 CT16Bn_CAP0 0 1 2 3 4 5 0x88 CT16Bn_EM 0 1 2 3 4 5 0x8C CT16Bn_EMC 1 0x90 CT16Bn_PWMCTRL 0 1 2 3 4 5 0x98 CT16Bn_PWMENB 1 0xA0 CT16Bn_PWMIOENB 1 0xA4 CT16Bn_RIS 0 1 2 3 4 5 0xA8 CT16Bn_IC 0...

Page 121: ...e counter reset 1 Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK This is cleared by HW when the counter reset operation finishes R W 0 0 CEN Counter E...

Page 122: ...me Description Attribute Reset 31 16 Reserved R 0 15 0 TC 15 0 Timer Counter R W 0 10 8 5 CT16Bn Prescale register CT16Bn_PRE n 0 1 2 3 4 5 Address Offset 0x08 Bit Name Description Attribute Reset 31...

Page 123: ...ng PCLK edges can increment Timer s Prescale Counter PC or clear PC and increment Timer Counter TC 00 Timer Mode every rising PCLK edge 01 Counter Mode TC is incremented on rising edges on the CAP0 in...

Page 124: ...and PC will stop and CEN bit will be cleared if MR0 matches TC 0 Disable 1 Enable R W 0 1 MR0RST Enable reset TC when MR0 matches TC 0 Disable 1 Enable R W 0 0 MR0IE Enable generating an interrupt ba...

Page 125: ...he TC 0 Disable 1 Enable R W 0 10 8 10CT16Bn Match Control register CT16Bn_MCTRL n 1 Address Offset 0x14 Note When the dead band function is enabled in Center aligned mode and MR12RST 1 CT16B1_PWMxN w...

Page 126: ...hen MR5 matches TC 0 Disable 1 Enable R W 0 15 MR5IE Enable generating an interrupt when MR5 matches the value in the TC 0 Disable 1 Enable R W 0 14 MR4STOP Stop MR4 TC and PC will stop and CEN bit wi...

Page 127: ...TC 15 0 will be reloaded from CT16Bn_MR12 after resetting counter System will reset TC refer to MR12RST ONLY in Center aligned mode Bit Name Description Attribute Reset 31 9 Reserved R 0 8 MR12STOP S...

Page 128: ...ettings in the CT16Bn_MCTRL register Bit Name Description Attribute Reset 31 24 PWMKEY 7 0 PWM register key Read as 0 When writing to the register you must write 0x5A to PWMKEY otherwise behaviour of...

Page 129: ...behaviour of writing to the register is ignored W 0 23 16 Reserved R 0 15 0 MR 15 0 Timer counter match value R W 0 10 8 17CT16Bn Capture Control register CT16Bn_CAPCTRL n 0 1 2 3 4 5 Address Offset...

Page 130: ...h a device pin and may be loaded with the counter timer value when a specified event occurs on that pin The settings in the Capture Control register determine whether the capture function is enabled a...

Page 131: ...0 CT16Bn_PWM3 pin is HIGH 11 Toggle CT16Bn_PWM3 pin R W 0 9 8 EMC2 1 0 Determines the functionality of CT16Bn_PWM2 when MR2 TC 00 Do Nothing 01 CT16Bn_PWM2 pin is LOW 10 CT16Bn_PWM2 pin is HIGH 11 Tog...

Page 132: ...EMC1 1 0 Determines the functionality of CT16Bn_PWM1 when MR1 TC 00 Do Nothing 01 CT16Bn_PWM1 pin is LOW 10 CT16Bn_PWM1 pin is HIGH 11 Toggle CT16Bn_PWM1 R W 0 5 4 EMC0 1 0 Determines the functionali...

Page 133: ...ve the state of CT16Bn_PWM6 output R W 0 5 EM5 When EMC5 00b and MR5 TC this bit will drive the state of CT16Bn_PWM5 output R W 0 4 EM4 When EMC4 00b and MR4 TC this bit will drive the state of CT16Bn...

Page 134: ...8 TC 00 Do Nothing 01 CT16Bn_PWM8 pin is LOW 10 CT16Bn_PWM8 pin is HIGH 11 Toggle CT16Bn_PWM8 R W 0 15 14 EMC7 1 0 Determines the functionality of CT16Bn_PWM7 when MR7 TC 00 Do Nothing 01 CT16Bn_PWM7...

Page 135: ...configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared Bit Name Description Attribute Reset 31 24 PWMKEY 7 0 PWM...

Page 136: ...CT16Bn_PWM1 R W 0 0 PWM0EN PWM0 enable 0 CT16Bn_PWM0 is controlled by EMC0 1 PWM mode is enabled for CT16Bn_PWM0 R W 0 10 8 24CT16Bn PWM Control register CT16Bn_PWMCTRL n 3 4 Address Offset 0x98 The...

Page 137: ...can be in dependently set to perform either as PWM output or as match output whose function is controlled by CT16Bn_EM register For CT16B1 a maximum of 12 single edge controlled PWM outputs can be sel...

Page 138: ...R4 during Up counting period 01 PWM mode 2 PWM4 is 1 when TC MR4 during Up counting period 10 PWM4 is forced to 0 11 PWM4 is forced to 1 R W 0 7 6 PWM3M0DE 1 0 PWM3 output mode 00 PWM mode 1 PWM3 is 0...

Page 139: ...WM6 enable 0 CT16Bn_PWM6 is controlled by EMC6 1 PWM mode is enabled for CT16Bn_PWM6 R W 0 5 PWM5EN PWM5 enable 0 CT16Bn_PWM5 is controlled by EMC5 1 PWM mode is enabled for CT16Bn_PWM5 R W 0 4 PWM4EN...

Page 140: ...M5IOEN CT16Bn_PWM5 GPIO selection bit 0 CT16Bn_PWM5 pin act as GPIO 1 CT16Bn_PWM5 pin act as match output and output signal depends on PWM5EN bit R W 0 4 PWM4IOEN CT16Bn_PWM4 GPIO selection bit 0 CT16...

Page 141: ...ntroller if the corresponding bit in the CT16Bn_IE register is set Bit Name Description Attribute Reset 31 6 Reserved R 0 5 MR9IF Interrupt flag for match channel 9 0 No interrupt on match channel 9 1...

Page 142: ...0 No interrupt on match channel 5 1 Interrupt requirements met on match channel 5 R 0 4 MR4IF Interrupt flag for match channel 4 0 No interrupt on match channel 4 1 Interrupt requirements met on match...

Page 143: ...ear MR8IF bit W 0 7 MR7IC 0 No effect 1 Clear MR7IF bit W 0 6 MR6IC 0 No effect 1 Clear MR6IF bit W 0 5 MR5IC 0 No effect 1 Clear MR5IF bit W 0 4 MR4IC 0 No effect 1 Clear MR4IF bit W 0 3 MR3IC 0 No e...

Page 144: ...t same High signal during dead band period 10 CT16Bn_PWM1N pin outputs the inverse signal with dead band of CT16Bn_PWM1 but same Low signal during dead band period 11 CT16Bn_PWM1N pin outputs the same...

Page 145: ...to the register you must write 0x5A to PWMKEY otherwise behaviour of writing to the register is ignored W 0 23 10 Reserved R 0 9 0 DB 9 0 Count of PWMmN output dead band period time PWMmN output dead...

Page 146: ...g and setup the Watchdog timer operating mode in WDT_CFG register 4 The Watchdog should be fed again by writing 0x55AA to WDT_FEED register before the Watchdog counter underflows to prevent reset or i...

Page 147: ...o Controller SONiX TECHNOLOGY CO LTD Page 147 Version 1 1 11 2 BLOCK DIAGRAM WDT_FEED WDT_TC 128 8 bit Down Counter WDINT WDTIE WDTEN WDT_PCLK Feed OK Feed Watchdog Enable Counter Reload Counter under...

Page 148: ...y when WDTIE 1 R W 0 1 WDTIE Watchdog interrupt enable 0 Watchdog timeout will cause a chip reset Watchdog reset mode Watchdog counter underflow will reset the MCU and will clear the WDTINT flag 1 Wat...

Page 149: ...s Offset 0x0C Bit Name Description Attribute Reset 31 16 WDKEY Watchdog register key Read as 0 When writing to the register you must write 0x5AFA to WDKEY otherwise behavior of writing to the register...

Page 150: ...nter and Divider Cold boot Three dedicated enabled interrupt lines Seconds interrupt generating a periodic interrupt signal with a programmable period length up to 1 second 12 3 FUNCTIONAL DESCRIPTION...

Page 151: ...80 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 151 Version 1 1 12 4 BLOCK DIAGRAM RTC_SECCNT SRC_SEL ELS_XTAL ILRC SEC_CNT_CLK RTC_SECCNTV SECIF RTCEN SECIE SECOND Interrupt...

Page 152: ...Description Attribute Reset 31 1 Reserved R 0 0 CLKSEL RTC clock source selection HW will reset SEC_CNT and ALM_CNT when changing the value 0 ILRC 1 ELS X TAL R W 0 12 5 3 RTC Interrupt Enable registe...

Page 153: ...20 Reserved R 0 19 0 SECCNTV 19 0 RTC second counter reload value Update this register will reset RTC_SECCNT register The zero value is not recommended and will be replaced with default value 0x8000...

Page 154: ...l data 13 2 FEATURES Compatible with Motorola SPI bus Synchronous Serial Communication Supports master or slave operation 8 frame FIFO for both transmitter and receiver 4 bit to 16 bit frame Maximum S...

Page 155: ...control bit is HIGH a steady state high value is placed on the CLK pin when data is not being transferred The CPHA clock phase bit controls the phase of the clock on which data is sampled When CPHA 1...

Page 156: ...TA LSB MSB LSB 1 2 3 4 5 6 7 8 SPI 13 4 2 2 MULTI FRAME CS DATA F0 msb F0 F0 F0 lsb F1 msb F1 F1 F1 lsb SCK SCK SCK SCK CPOL 0 CPHA 1 CPOL 1 CPHA 0 CPOL 1 CPHA 1 CPOL 0 CPHA 0 SPI 13 5 AUTO SEL The Au...

Page 157: ...2 0 TX FIFO Threshold level 000 TX FIFO threshold level 0 001 TX FIFO threshold level 1 111 TX FIFO threshold level 7 R W 000b 11 8 DL 3 0 Data length DL 3 0 1 0000 0001 Reversed 0010 data length 3 11...

Page 158: ...r register SPIn_CLKDIV n 0 1 Address Offset 0x08 Bit Name Description Attribute Reset 31 8 Reserved R 0 7 0 DIV 7 0 SPIn clock divider 0 SCK SPIn_PCLK 2 1 SCK SPIn_PCLK 4 2 SCK SPIn_PCLK 6 X SCK SPIn_...

Page 159: ...In_IE register This register indicates the status for SPI control raw interrupts An SPI interrupt is sent to the interrupt controller if the corresponding bit in the SPIn_IE register is set Bit Name D...

Page 160: ...Data register SPIn_DATA n 0 1 Address Offset 0x1C Bit Name Description Attribute Reset 31 16 Reserved R 0 15 0 DATA 15 0 Write SW can write data to be sent in a future frame to this register when TX_F...

Page 161: ...t Name Description Attribute Reset 31 1 Reserved R 0 1 DIR SPI data transfer direction 0 SPI1_DATA RX to SPI0_DATA TX when DMATCIE and DMAHTIE enable and trigger SPI0 interrupt 1 SPI0_DATA RX to SPI1_...

Page 162: ...DMA is enabled this register is read only indicating the remaining bytes to be transmitted Once the half transfer is completed CURCNT HTCNT and trigger DMATC interrupt R W 0xFFFFFFF 13 6 13SPI n DMA...

Page 163: ...Cortex M0 without interfering with other devices on the same I2C bus Standard I2C compliant bus interfaces may be configured as Master or Slave I2C Master features Clock generation Start and Stop gen...

Page 164: ...SN32F280 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 164 Version 1 1 14 4 WAVE CHARACTERISTICS SDA S START Signal P STOP Signal Data Change Allowed Data Change Allowed...

Page 165: ...4 D4 5 D3 6 D2 7 D1 P 9 D6 ACK_ 9 8 D0 D0 Write 1 to ACK bit Start Acknowledge sequence ACK from Master Receiving Data from Slave ACK_ is not sent Write 1 to STO bit Master terminal transfer Data shif...

Page 166: ...7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R W 0 ACK_ 1 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 P SDA SCL Transmission Data R W 1 D7 14 6 2 SLAVE RECEIVER MODE S Receiving Address ACK_ 1 A7 2 A6 3 A5 4 A4 5 A3...

Page 167: ...e I2C interface is in slave mode an internal STOP condition is generated but is not transmitted on the bus Note 1 I2CEN shall be set at last 2 HW will assign SCL0 SCL1 and SDA0 SDA1 pins as output pin...

Page 168: ...condition Timeout Data byte transmitted or received ACK Transmit or received NACK Transmit or received Bit Name Description Attribute Reset 31 16 Reserved R 0 15 I2CIF I2C Interrupt flag 0 I2C status...

Page 169: ...register I2Cn_SLVADDR0 n 0 1 Address Offset 0x10 Only used in slave mode In master mode this register has no effect If this register contains 0x00 the I2C will not acknowledge any address on the bus...

Page 170: ...Time SCLL 1 I2C0_PCLK cycle R W 0x04 14 7 9 I2C n Timeout Control register I2Cn_TOCTRL n 0 1 Address Offset 0x2C Timeout happens when Master Slave SCL remained LOW for TO 32 I2C0_PCLK cycle When I2C t...

Page 171: ...low speed data transfer and communicate with low speed peripheral devices The UART offers a very wide range of baud rates using a fractional baud rate generator 15 2 FEATURES Full duplex 2 wire async...

Page 172: ...tex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 172 Version 1 1 15 4 BLOCK DIAGRAM UART Baud Rate Generator RX DLL DLM UARTn_RB RSR TX UARTn_TH TSR UTXD URXD APB SCR INTERRUPT UARTn_IE UARTn_II U...

Page 173: ...AL MULVAL 4 Oversampling is 8 or 16 The value of the UARTn_FD register should not be modified while transmitting receiving data or data may be lost or corrupted The oversampling method can be selected...

Page 174: ...mmand If enabled the auto baud feature will measure the bit time of the receive data stream and set the divisor latch registers UARTn_DLM and UARTn_DLL accordingly Auto baud function is started by set...

Page 175: ...nter is reset and the RSR is reset The RSR baud rate is switched to the highest rate 2 A falling edge on URXD pin triggers the beginning of the start bit The rate measuring counter will start counting...

Page 176: ...Micro Controller SONiX TECHNOLOGY CO LTD Page 176 Version 1 1 bit1 bit3 bit4 bit5 bit6 Start bit7 Parity Stop URXD bit0 bit2 A 0x41 or a 0x61 START bit in USARTn_ABCTRL Start bit LSB of A or a Rate C...

Page 177: ...g register UARTn_TH n 0 1 2 3 Address Offset 0x00 This register is the byte of the UART TX FIFO The byte is the character in the TX FIFO and can be written via the bus interface The LSB represents the...

Page 178: ...ble 1 Enable R W 0 3 Reserved R 0 2 RLSIE Receive Line Status RLS interrupt enable bit The status of this interrupt can be read from UARTn_LS 4 1 0 Disable 1 Enable R W 0 1 THREIE THRE interrupt enabl...

Page 179: ...pt service routine Interrupt USARTn_II 3 0 Priority Interrupt Source Interrupt Reset RLS 0110 Highest Overrun error OE Parity error PE Framing error FE or Break interrupt BI Read UARTn_LS register RDA...

Page 180: ...ntains valid data 1 THR and TSR are empty R 1 5 THRE Transmitter Holding Register Empty flag THRE indicates that the UART is ready to accept a new character for transmission In addition this bit cause...

Page 181: ...at would indicate to the host that a read or write of this register has occurred Bit Name Description Attribute Reset 31 8 Reserved R 0 7 0 PAD 7 0 A readable writable byte R W 0 15 7 10UART n Auto ba...

Page 182: ...111 Baud rate pre scaler multiplier value is 16 for HW R W 0 3 0 DIVADDVAL 3 0 Baud rate generation pre scaler divisor value If this field is 0 fractional baud rate generator will not impact the UART...

Page 183: ...ries 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 183 Version 1 1 Other Reserved 0 UARTEN UART enable 0 Disable 1 Enable HW switches GPIO to UART pin according to MODE bits automatic...

Page 184: ...ed I2S and MSB justified data format supported 8 word 32 bit FIFO data buffers are provided Generate interrupt requests when buffer levels cross a programmable boundary Controls include reset stop and...

Page 185: ...4 1 I2S CLCOK CONTROL I2S_PCLK HCLK MCLK_I MCLK_ SOURCE MCLKDIV MCLK MCLKO_EN MCLK_O MCLK_SEL BCLKDIV BCLK_O BCLK_I MS BCLK BCLK_O I2S DIV I2S_MCLK 16 4 2 I2S BLOCK DIAGRAM I2S CLOCK CONTROL 8 x 32 bi...

Page 186: ...SB Left justified Data Format Channel Length Data Length msb BCLK SD WS lsb 0 0 0 msb lsb 0 0 0 msb Channel length Left Channel length Right Data length I2S msb BCLK SD WS lsb 0 0 0 msb lsb 0 0 0 msb...

Page 187: ...rtex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 187 Version 1 1 Channel Length Data Length msb BCLK SD WS lsb msb lsb msb I2S msb BCLK SD WS lsb msb lsb msb Left Justified msb BCLK SD WS lsb msb...

Page 188: ...88 Version 1 1 16 5 2 I2S FIFO OPERAION 16 5 2 1 MONO 8bit N 3 N 2 N 1 N N 7 N 6 N 5 N 4 16bit N 1 N N 3 N 2 24 bit N N 1 32 bit N N 1 16 5 2 2 STEREO 8bit RIGHT 1 LEFT 1 RIGHT LEFT RIGHT 3 LEFT 3 RIG...

Page 189: ...FIFO threshold level n R W 0x3 15 Reserved R 0 14 12 TXFIFOTH 2 0 TX FIFO Threshold level 0 TX FIFO threshold level 0 1 TX FIFO threshold level 1 n TX FIFO threshold level n R W 0x3 11 10 DL 1 0 Data...

Page 190: ...7 Reserved R 0 16 CLKSEL I2S clock source selection 0 HCLK 1 EHS XTAL R W 0 15 8 BCLKDIV 7 0 BCLK divider 0 BCLK MCLK 2 1 BCLK MCLK 4 2 BCLK MCLK 6 3 BCLK MCLK 8 n BCLK MCLK 2 n 2 R W 1 7 5 Reserved R...

Page 191: ...F RX FIFO threshold flag 0 RXFIFOLV RXFIFOTH 1 RXFIFOLV RXFIFOTH R 0 6 TXFIFOTHF TX FIFO threshold flag 0 TXFIFOLV TXFIFOTH 1 TXFIFOLV TXFIFOTH R 1 5 2 Reserved R 0 1 RIGHTCH Current channel status 0...

Page 192: ...lag 0 No TX FIFO overflow 1 TX FIFO overflow TX FIFO is full and still being written R 0 3 0 Reserved R 0 16 6 6 I2S n Interrupt Clear register I2S_IC n 0 1 Address Offset 0x14 Bit Name Description At...

Page 193: ...768kHz oscillator crystal or RC type and controlled by LCDCKS bit In LCD mode the LCD builds in one internal bias circuit to adjust LCD power and bias voltage There are 40 pin GPIO shared with COM pi...

Page 194: ...shared with GPI O pins and unused segment and common pins can be used as GPIO pins 4 Support 1 3 bias voltage 5 Support 1 4 duty 1 6 duty 1 7 duty and 1 8 duty 6 Configurable frame frequency 7 Embedde...

Page 195: ...from the LCD bias generator The bias switch is controlled by LCD COM and SEG output control In LCD static mode the bias switch of COM and SEG pins is disabled The selected COM and SEG pins switch to...

Page 196: ...es RLCD for difference VLCD controlled by LCDBIA 2 0 bits The RLCD is from 17 65K to 300K The final 4 level LCD bias voltage source is VLCD V2 V1 GND and supply to LCD COM and SEG pins When the static...

Page 197: ...1 0 00 16 01 32 10 64 11 128 ILRC 32000Hz 2000 1000 500 250 ELS XTAL 32768Hz 2048 1024 512 256 LCD Frame rate Hz LCDRATE 1 0 00 16 01 32 10 64 11 128 ILRC 32000Hz 4 COM mode 250 Hz 125 Hz 62 5 Hz 31 2...

Page 198: ...D mode with 4 COM mode COM0 pin COM1 pin COM2 pin COM3 pin SEG0 pin 0101b SEG1 pin 0000b COM0 SEG0 Segment is on COM1 SEG1 Segment is off 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1...

Page 199: ...1 pin COM2 pin COM3 pin SEG0 pin 000101b SEG1 pin 000000b COM0 SEG0 Segment is on COM1 SEG1 Segment is off 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2...

Page 200: ...in COM3 pin SEG0 pin 0000101b SEG1 pin 0000000b COM0 SEG0 Segment is on COM1 SEG1 Segment is off 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD V1 V2...

Page 201: ...EG0 pin 00000101b SEG1 pin 00000000b COM0 SEG0 Segment is on COM1 SEG1 Segment is off 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD 0V V1 V2 VLCD V1 V2 VLCD 0V V1...

Page 202: ...SONiX TECHNOLOGY CO LTD Page 202 Version 1 1 Waveform in static mode with 4 COM mode COM0 pin COM1 pin COM2 pin COM3 pin SEG0 pin 0101b SEG1 pin 0000b 0V Vcc 0V Vcc 0V Vcc 0V Vcc 0V Vcc 0V Vcc 1 Fram...

Page 203: ...mode or idle status by LCDIDLE bit To output next frame is to set LCDEN bit by program again SEG pin LCDSFM 1 and LCDEN 1 LCDEN 0 automatically The pin exchanges to last GPIO mode LCDEN 0 LCDEN 0 LCDS...

Page 204: ...SEG11 SEG7 SEG3 COM7 30 COM6 29 COM5 28 COM4 27 COM3 26 COM2 25 COM1 24 COM0 23 SEG38 SEG34 SEG30 SEG26 SEG22 SEG18 SEG14 SEG10 SEG6 SEG2 COM7 22 COM6 21 COM5 20 COM4 19 COM3 18 COM2 17 COM1 16 COM0...

Page 205: ...ank control bit 0 Normal display 1 All LCD dots off R W 0 10 LCDCKS LCD clock source selection 0 ILRC 1 ELS XTAL R W 0 9 8 LCDCOM 1 0 Duty selection 00 1 4 duty COM0 COM1 COM2 and COM3 organize 1 fram...

Page 206: ...VCC 1010 VLCD 0 67 VCC 1011 VLCD 0 63 VCC 1100 VLCD 0 60 VCC 1101 VLCD 0 57 VCC 1110 VLCD 0 53 VCC 1111 VLCD 0 50 VCC R W 0 0 LCDENB LCD driver enable bit 0 Disable 1 Enable R W 0 17 11 2LCD Frame Co...

Page 207: ...0 SEGx enable bit x 0 31 0 Disable SEGx 1 Enable SEGx R W 0 17 11 5LCD SEG Select register LCD_SEGSEL2 Address offset 0x10 Bit Name Description Attribute Reset 31 8 Reserved R 0 7 SEG39EN SEG39 enable...

Page 208: ...OM7 R W 0 23 16 SEG6 7 0 SEG6 data for COM0 COM7 R W 0 15 8 SEG5 7 0 SEG5 data for COM0 COM7 R W 0 7 0 SEG4 7 0 SEG4 data for COM0 COM7 R W 0 17 11 8LCD SEG Memory register 2 LCD_SEGM2 Address Offset...

Page 209: ...SEG23 data for COM0 COM7 R W 0 23 16 SEG22 7 0 SEG22 data for COM0 COM7 R W 0 15 8 SEG21 7 0 SEG21 data for COM0 COM7 R W 0 7 0 SEG20 7 0 SEG20 data for COM0 COM7 R W 0 17 11 12 LCD SEG Memory regist...

Page 210: ...SEG35 data for COM0 COM7 R W 0 23 16 SEG34 7 0 SEG34 data for COM0 COM7 R W 0 15 8 SEG33 7 0 SEG33 data for COM0 COM7 R W 0 7 0 SEG32 7 0 SEG32 data for COM0 COM7 R W 0 17 11 15 LCD SEG Memory regist...

Page 211: ...exed modes However for the non multiplexed 8 bit address mode both the address and data uses these 16 AD pins If more address bits or data bits are needed an external latch can be used to support up t...

Page 212: ...on 1 1 WE O Write enable ALE O Addresses latch enable ARDY I Ready Busy pin Depends on GPIOn_CFG UB O Upper byte enable LB O Lower byte enable 18 4 BLOCK DIAGRAM AHB Bus EBI Register Block EBI Block E...

Page 213: ...N bit address and 8 bit data is supported The address is located on the N bits of the A lines and the data uses the lower 8 bits AD lines A1D8 Mode is also called 8080 8 bit mode Read timing waveform...

Page 214: ...s whereas the 16 bit width of external device is addressed in words 16 bit in case of a 16 bit external device width the EBI will internally use HADDR N 1 to generate the address EBI_A N 1 0 for exter...

Page 215: ...the AD and A pins An EBI address latch setup diagram is shown as below EBI Device External Asynchronous Device EBI A Address MSBs Control Latch EBI AD Address LSBs Data ALE At the start of the transa...

Page 216: ...e cycle state of EBI bus The RDHOLD timing parameter is for the bus turn around time and should be programmed to ensure enough time for the characteristics of an external device The default setting fo...

Page 217: ...on width to external device transactions which matches the external bus capabilities of the device If the AHB master CPU transaction width is larger than the external bus transaction width The EBI wil...

Page 218: ...rite 2 x 8 bit Write 1 x 16 bit Write 1 x 16 bit Write 32 bit Read 4 x 8 bit Read 2 x 16 bit Read 2 x 16 bit Read 32 bit Write 4 x 8 bit Write 2 x 16 bit Write 2 x 16 bit Write External Bus Width Acce...

Page 219: ...low external devices when it is enabled ARDYNEN bit 1 in the EBI_CTRL register EBI_ARDY can be configured by the polarity of this signal with the ARDYPOL bit in the EBIPR register If the ARDYPOL bit i...

Page 220: ...I Flash T1 SHALL be more than or equal to the time for MCU to transmit data via A1D16 T2 In A1D8 mode the MCU will receive 2 8 bit data from SPI Flash and transmit 2 8 bit data to panel directly and t...

Page 221: ...SN32F280 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 221 Version 1 1 18 6 2 DMA DATA FORMAT A1D8...

Page 222: ...SN32F280 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 222 Version 1 1 A1D16...

Page 223: ...ARDY1EN ARDY of Bank 1 enable bit 0 Disable EBI bank 1 ARDY function 1 Enable EBI bank 1 ARDY function R W 0 16 ARDY0EN ARDY of Bank 0 enable bit 0 Disable EBI bank 0 ARDY function 1 Enable EBI bank...

Page 224: ...set AL0 3 0 11 8080 Also need to set BK8080MODE0 R W 0 18 7 2 EBI Address Length Control register EBI_ALCTRL Address offset 0x04 Bit Name Description Attribute Reset 31 16 Reserved R 0 15 12 AL3 3 0 E...

Page 225: ...8 0x2C RDSETUP 3 0 is the number of cycles for the address setup before EBI_OE is asserted RDSTRB 5 0 is the number of cycles the EBI_OE is held active after the specified number of cycles the data is...

Page 226: ...Reserved R 0 4 ARDYPOL Asynchronous Ready Polarity 0 ARDY is active low 1 ARDY is active high R W 0 3 ALEPOL Address Latch Polarity 0 ALE is active low idle high 1 Reserved R 0 2 WEPOL Write Enable P...

Page 227: ...BI read write error flag 0 Nor error 1 Read Write error R 0 2 SMRSTIF EBI state machine resetting flag 0 Not resetting 1 EBI is resetting the state machine R 0 1 ACCDISIF EBI accessing the disabled ba...

Page 228: ...DMACNT Address offset 0x64 This register can only be written when the DMA is disabled Once the DMA is enabled this register is read only indicating the remaining bytes to be transmitted Once the trans...

Page 229: ...LTD Page 229 Version 1 1 18 7 14EBI DMA Current Transfer Data Counter register EBI_CURCNT Address offset 0x6C Bit Name Description Attribute Reset 31 28 Reserved R 0 27 0 CURCNT 27 0 This field indic...

Page 230: ...stored at a given memory location 19 2 FEATURES 1 Support CRC 32 polynomial X 32 X 26 X 23 X 22 X 16 X 12 X 11 X 10 X 8 X 7 X 5 X 4 X 2 X 1 CRC 16 polynomial X 16 X 15 X 2 1 CRC 16 CCITT polynomial X...

Page 231: ...ROM except the last page This bit is set only by SW and reset by HW 0 Stop Finish operation R W 0 2 RESET Reset bit 0 No effect 1 Reset the CRC calculation circuit Reset the initial seed value and BUS...

Page 232: ...d 6 configurable endpoints for interrupt bulk transfer Integrated USB transceiver 5V to 3 3V regulator output for D 1 5K ohm internal resistor pull up 20 2 FEATURES 1 Conforms to USB specifications Ve...

Page 233: ...ction active The USB_EPnBUFOS block is used to control each endpoint s effective starting address The principles to access USB SRAM are as below 1 Each EPnBUFOS setting must be word aligned with 2 LSB...

Page 234: ...appropriate bit of registers Firmware is required to handle the rest of the following tasks 1 Coordinate enumeration by decoding USB device requests 2 Fill and empty the FIFOs 3 Reset Suspend Resume...

Page 235: ...packet followed by a DATA packet to address 0 assigning a new USB address to the device 5 Firmware stores the new address in its USB Device Address Register after the no data control sequence complet...

Page 236: ...4 Buffer Offset Register 0x0000_0100 USB_EP5BUFOS 0x58 R W USB Endpoint 5 Buffer Offset Register 0x0000_0140 USB_EP6BUFOS 0x5C R W USB Endpoint 6 Buffer Offset Register 0x0000_0180 USB_FRMNO 0x60 R US...

Page 237: ...is detected 1 Bus reset signal is detected Cleared by write 1 to USB_INSTSC 31 R 0 30 BUS_SUSPEND USB Bus Suspend signal 3ms idle state flag 0 No bus suspend is detected 1 Bus suspend is detected R 0...

Page 238: ...ransaction 1 Endpoint 4 ACK transaction completes Cleared by write 1 to USB_INSTSC 11 R 0 10 EP3_ACK Endpoint 3 ACK transaction flag 0 No Endpoint 3 ACK transaction 1 Endpoint 3 ACK transaction comple...

Page 239: ...ct 1 Clear EP0_OUT bit W 0 20 EP0_IN_STALLC 0 No effect 1 Clear EP0_IN_STALL bit W 0 19 EP0_OUT_STALLC 0 No effect 1 Clear EP0_OUT_STALL bit W 0 18 ERR_SETUPC 0 No effect 1 Clear ERR_SETUP bit W 0 17...

Page 240: ...stor R W 0 28 SIE_EN USB serial interface engine enable 0 Disable USB SIE function 1 Enable USB SIE function R W 0 27 ESD_EN USB ESD protection enable 0 Disable ESD protection 1 Enable ESD protection...

Page 241: ...nsaction completes the ENDP_STATE will automatically return to NAK state 10 11 INOUT_STALL Device will handshake STALL to both IN or OUT token ENDP_STATE will automatically return to NAK state after U...

Page 242: ...e device will handshake STALL to OUT token and the following data0 1 R W 0 28 7 Reserved 0 6 0 ENDP_CNT 6 0 Endpoint Byte Count For IN direction usage the ENDP_CNT indicates the byte count to be uploa...

Page 243: ...escription Attribute Reset 31 11 Reserved R 0 10 0 FRAME_NO 10 0 The 11 bit frame number of the Start Of Frame SOF packet This number is updated by H W automatically when SOF packet is received R 0 20...

Page 244: ...0x7C Reset value 0x0000 0000 Bit Name Description Attribute Reset 31 0 RWDATA 31 0 Data to be read or written from to USB FIFO R W 0 20 9 17USB Read Write Status Register USB_RWSTATUS Address Offset...

Page 245: ...20 9 20USB Read Write Status Register 2 USB_RWSTATUS2 Address Offset 0x8C Reset value 0x0000 0000 Bit Name Description Attribute Reset 31 2 Reserved R 0 1 R_STATUS Read status of USB FIFO If F W is t...

Page 246: ...memory map of chip The high performance Flash memory module in chip has the following key features Memory organization the Flash memory is organized as a User ROM Boot ROM User ROM Up to 128K Bytes d...

Page 247: ...h module through dedicated read senses and provides the requested data The read interface consists of a read controller on one side to access the Flash memory and an AHB interface on the other side to...

Page 248: ...omes effective only after the MCU has been Reboot User ROM CS0 CS1 CS2 Description WRITER Read O X X Erase O O O WRITER will change the CS level to CS0 Program O O O FW EEPROM emulation Read O O O Era...

Page 249: ...mory can be erased page by page or completely Mass Erase 21 8 3 1 PAGE ERASE A page of the Flash memory can be erased using the Page Erase feature of the FMC To erase a page the procedure below should...

Page 250: ...Attribute Reset 31 3 Reserved R 0 2 ERR Error flag 0 Read No error Write Clear this flag 1 Set by HW when Start to Erase Program and find that the address is over page boundary Start to Erase Program...

Page 251: ...tions this should be updated by SW to indicate the data to be programmed Bit Name Description Attribute Reset 31 0 DATA 31 0 Data to be programmed R W 0 21 11 5Flash Address register FLASH_ADDR Addres...

Page 252: ...troller SONiX TECHNOLOGY CO LTD Page 252 Version 1 1 0x0000 0000 0x0001 0000 0x0002 0000 User ROM 1 User ROM 2 Bit Name Description Attribute Reset 31 16 UR2CHKSUM 15 0 Checksum of User ROM 2 R 0 15 0...

Page 253: ...power modes work internal to the ARM Cortex M0 CPU and this ripples through the entire system These differences mean that power measurements should not be made while debugging the results will be high...

Page 254: ...PULL UP DOWN RESISTORS on SWD PINS To avoid any uncontrolled IO levels the device embeds internal pull up and pull down resistor on the SWD input pins NJTRST Internal pull up SWDIO JTMS Internal pull...

Page 255: ...Kit SN LINK V3 USB cable to provide communications between the SN LINK V3 and PC IDE Tools KEIL RVMDK SONiX 32 bit MCU Starter Kit SN LINK V3 IDE Tools SONiX 32 bit series Embedded ICE Emulator Featur...

Page 256: ...bit MCU It debugs and programs based on SWD protocol In addition to debugger functions the SN LINK V3 also may be used as a programmer to load firmware from PC to MCU for engineering production even...

Page 257: ...n It is a simple platform to develop application as target board not ready The starter kit can be replaced by target board because of integrated SWD debugger circuitry JP9 Micro USB connector JP3 USB...

Page 258: ...e 3 1 5 0 5 25 V VDD rise rate VPOR VDD rise rate to ensure internal power on reset 0 05 V ms Power Consumption Supply Current Idd1 Normal mode System clock 12MHz 1 2 3 2 9 mA System clock 24MHz 1 3 4...

Page 259: ...VCM 1 2 VDD 5 5 mV Response Time TRS Normal mode Positive input voltage 1 2 Vdd Negative input voltage transitions from Vss to Vdd 50 100 ns Output Slew Rate Time TOSR Vo rising Vss Vdd or falling Vdd...

Page 260: ...ts driven LOW and pull up resistors disabled and VDD 5V 7 IHRC and ILRC are enabled external X tal is disabled and PLL is enabled 8 IHRC is disabled ILRC is enabled and PLL is disabled 24 3 CHARACTERI...

Page 261: ...N32F289F SN32F288F SN32F287F MP PRO Writer Connector Number Name Number Pin Number Pin Number Pin Number Pin Number Pin 1 VDD 57 80 VDD 48 64 VDD 36 48 VDD 2 GND 79 VSS 63 VSS 47 VSS 3 CLK 51 P3 1 42...

Page 262: ...SN32F280 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 262 Version 1 1 2 2 26 6 6PACKAGE INFORMATION 26 1 LQFP 80 PIN...

Page 263: ...SN32F280 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 263 Version 1 1 26 2 LQFP 64 PIN...

Page 264: ...SN32F280 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 264 Version 1 1 26 3 LQFP 48 PIN...

Page 265: ...CU production line This note lists the marking definitions of all 32 bit MCU for order or obtaining information 27 2 MARKING INDETIFICATION SYSTEM Title SONiX 32 bit MCU Production ROM Type F Flash me...

Page 266: ...ARKING EXAMPLE Name ROM Type Device Package Temperature Material SN32F289FG Flash memory 289 LQFP 40 85 Green Package SN32F288FG Flash memory 289 LQFP 40 85 Green Package SN32F287FG Flash memory 289 L...

Page 267: ...roller SONiX TECHNOLOGY CO LTD Page 267 Version 1 1 27 4 DATECODE SYSTEM X X X X XXXXX Year Month 1 January 2 February 9 September A October B November C December SONiX Internal Use Day 1 01 2 02 9 09...

Page 268: ...hould Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors...

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