SN32F280 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 59
Version 1.1
3.2.3.5
Bypass Mode
Clock Source
H/W Configuration
Description
External clock source
(Bypass)
In Bypass mode, the external clock signal (square,
sinus or triangle) with ~50% duty cycle must be
provided to drive the XIN/LXIN pin while the
XOUT/LXOUT pin should be the inverse of the
input clock signal.
EHS X’tal can have a frequency of up to 25 MHz.
Select this mode by setting EHSEN bit in
Block Control register (SYS0_ANBCTRL)
ELS X’TAL must have a frequency of 32.768 KHz.
You select this mode by setting ELSEN bit in
Analog Block Control register (SYS0_ANBCTRL)
External X’TAL
(EHS/ELS X’TAL)
The 10
to 25 MHz EHS X’TAL has the advantage
of producing a very accurate rate on the main
clock
ELS
X’TAL must have a frequency of 32.768 KHz.
3.2.4 SYSTEM CLOCK (SYSCLK) SELECTION
After a system reset, the IHRC is selected as system clock. When a clock source is used directly or through the PLL as
system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay
or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source is ready.
Ready bits in
register indicate which clock(s) is (are) ready and SYSCLKST bits in
register indicate which clock is currently used as system clock.
3.2.5 CLOCK-OUT CAPABITITY
The MCU clock output (CLKOUT) capability allows the clock to be output onto the external CLKOUT pin. The
configuration registers of the corresponding GPIO port must be programmed in alternate function mode.
One of 6 clock signals can be selected as clock output:
1. HCLK
2. IHRC
3. ILRC
4. PLL clock output
5.
ELS X’TAL
6.
EHS X’TAL
The selection is controlled by the CLKOUTSEL bits in
