K5D2G13ACM-D075
Revision 1.0
December 2006
17
MCP MEMORY
NAND Flash Technical Notes
(Continued)
Copy-Back Operation with EDC & Sector Definition for EDC
Generally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source
page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate
bit errors.
device supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be
performed on either whole page(2112byte) or sector(528byte).
Modifying the data of a sector by Random Data Input before
Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modifi-
cation smaller than a sector corrupts the on-chip EDC codes.
A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte
spare area.
"A" area
512 Byte
(1’st sector)
"H" area
(4’th sector)
Main Field (2,048 Byte)
16 Byte
"G" area
(3’rd sector)
16 Byte
"F" area
(2’nd sector)
16 Byte
"E" area
(1’st sector)
16 Byte
"B" area
512 Byte
(2’nd sector)
"C" area
512 Byte
(3’rd sector)
"D" area
512 Byte
(4’th sector)
Spare Field (64 Byte)
Table 2. Definition of the 528-Byte Sector
Sector
Main Field (Column 0~2,047)
Spare Field (Column 2,048~2,111)
Area Name
Column Address
Area Name
Column Address
1’st 528-Byte Sector
"A"
0 ~ 511
"E"
2,048 ~ 2,063
2’nd 528-Byte Sector
"B"
512 ~ 1,023
"F"
2,064 ~ 2,079
3’rd 528-Byte Sector
"C"
1,024 ~ 1,535
"G"
2,080 ~ 2,095
4’th 528-Byte Sector
"D"
1,536 ~ 2,047
"H"
2,096 ~ 2,111
Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most
significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the
LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0.
From the LSB page to MSB page
DATA IN: Data (1)
Data (64)
(1)
(2)
(3)
(32)
(64)
Data register
Page 0
Page 1
Page 2
Page 31
Page 63
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (64)
(2)
(32)
(3)
(1)
(64)
Data register
Page 0
Page 1
Page 2
Page 31
Page 63
Addressing for program operation
:
:
:
:
Summary of Contents for SC32442B54
Page 1: ...SC32442B54 USER S MANUAL Revision 1 0 ...
Page 43: ...PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR 1 42 NOTES ...
Page 59: ...PROGRAMMER S MODEL SC32442B RISC MICROPROCESSOR 2 16 NOTES ...
Page 123: ...ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR 3 64 NOTES ...
Page 167: ...THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR 4 44 NOTES ...
Page 187: ...MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR 5 20 NOTES ...
Page 250: ...DMA SC32442B RISC MICROPROCESSOR 8 14 NOTES ...
Page 308: ...PWM TIMER SC32442B RISC MICROPROCESSOR 10 20 NOTES ...
Page 330: ...UART SC32442B RISC MICROPROCESSOR 11 22 NOTES ...
Page 417: ...SC32442B RISC MICROPROCESSOR LCD CONTROLLER 15 45 NOTES ...
Page 427: ...ADC AND TOUCH SCREEN INTERFACE SC32442B RISC MICROPROCESSOR 16 10 NOTES ...
Page 511: ...BUS PRIORITIES SC32442B RISC MICROPROCESSOR 24 2 NOTES ...
Page 562: ...K5D2G13ACM D075 Revision 1 0 December 2006 7 MCP MEMORY 2Gb 256Mb x8 NAND Flash Memory A Die ...
Page 599: ...K5D2G13ACM D075 Revision 1 0 December 2006 44 MCP MEMORY 512Mb 16Mb x32 Mobile SDRAM C Die ...