Samsung SC32442B54, User Manual

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SC32442B RISC MICROPROCESSOR PRODUCT OVERVIEW
1-27
Table 1-3. SC32442B Signal Descriptions (Sheet 5 of 6)
Signal Input/Output Description
Reset, Clock & Power
XTOpll AO Crystal Output for internal osc circuit.
When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK
source.
When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only.
When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only.
If it isn't used, it has to be a floating pin.
MPLLCAP AI Loop filter capacitor for main clock.
UPLLCAP AI Loop filter capacitor for USB clock.
XTIrtc AI 32 kHz crystal input for RTC. If it isn’t used, it has to be High (VDDRTC).
XTOrtc AO 32 kHz crystal output for RTC. If it isn’t used, it has to be Float.
CLKOUT[1:0] O Clock output signal. The CLKSEL of MISCCR register configures the clock
output mode among the MPLL CLK, UPLL CLK, FCLK, HCLK, PCLK.
nRESET ST nRESET suspends any operation in progress and places SC32442B into a
known reset state. For a reset, nRESET must be held to L level for at least 4
OSCin after the processor power has been stabilized.
nRSTOUT O For external device reset control(nRSTOUT = nRESET & nWDTRST &
SW_RESET)
PWREN O 1.2V/1.3V core power on-off control signal
nBATT_FLT I Probe for battery state(Does not wake up at Sleep mode in case of low battery
state). If it isn’t used, it has to be High (VDDOP).
OM[3:2] I OM[3:2] determines how the clock is made.
OM[3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source.
OM[3:2] = 01b, Crystal is used for MPLL CLK source
and EXTCLK is used for UPLL CLK source.
OM[3:2] = 10b, EXTCLK is used for MPLL CLK source
and Crystal is used for UPLL CLK source.
OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source.
EXTCLK I External clock source.
When OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK
source.
When OM[3:2] = 10b, EXTCLK is used for MPLL CLK source only.
When OM[3:2] = 01b, EXTCLK is used for UPLL CLK source only.
If it isn't used, it has to be High (VDDOP).
XTIpll AI Crystal Input for internal osc circuit.
When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK
source.
When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only.
When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only.
If it isn't used, XTIpll has to be High (VDDOP).