Samsung SC32442B54, User Manual

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K5D2G13ACM-D075
Revision 1.0
December 2006
39
MCP MEMORY
R/B
85h
11h
t
DBSY
Add.(5Cycles)
Data 85h Data
I/Ox
Col. Add.1,2 & Row Add.1,2,3
Col. Add.1,2
Add.(2Cycles)
00h
R/B
Add.(5Cycles)
t
R
Source Address On Plane0
35h
I/Ox
Col. Add.1,2 & Row Add.1,2,3
00h
Add.(5Cycles)
Source Address On Plane1
35h
Col. Add.1,2 & Row Add.1,2,3
t
R
1
R/B
81h
10h
t
PROG
Add.(5Cycles) Data 85h Data
I/Ox
Col. Add.1,2 & Row Add.1,2,3
Col. Add.1,2
Add.(2Cycles)
1
2
2
Destination Address
A
0
~ A
11 :
Valid
A
12
~ A
17 :
Fixed ’Low’
A
18 :
Fixed ’Low’
A
19
~ A
28 :
Fixed ’Low’
Destination Address
A
0
~ A
11 :
Valid
A
12
~ A
17 :
Valid
A
18 :
Fixed ’High’
A
19
~ A
28 :
Valid
Figure 17. Two-Plane Copy-Back Program Operation with Random Data Input
Note
:
1. Copy-Back Program operation is allowed only within the same memory plane.
2. On the same plane, It’s prohibited to operate copy-back program from an odd address page(source page) to an even
address page(target page) or from an even address page(source page) to an odd address page(target page).
Therefore, the copy-back program is permitted just between odd address pages or even address pages.
3. EDC status Bits are not available during copy back for some bits or bytes modified by Random Data Input operation.
In case of the 528 byte plane unit modification, EDC status bits are available.
4
.
Any command between 11h and 81h is prohibited except 70h and FFh.
Note4