Samsung SC32442B54, User Manual

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K5D2G13ACM-D075
Revision 1.0
December 2006
37
MCP MEMORY
Figure 14. Two-Plane Page Program
80h 11h
Data
Input
Plane 0
(1024 Block)
Block 0
Block 2
Block 2046
Block 2044
80h
I/O
0 ~ 7
R/B
Address & Data Input 11h
81h 10h
t
DBSY
t
PROG
70h Address & Data Input
NOTE :1. It is noticeable that same row address except for A
18
is applied to the two blocks
81h 10h
Plane 1
(1024 Block)
Block 1
Block 3
Block 2047
Block 2045
Figure 15. Two-Plane Block Erase Operation
60h
I/O
X
R/B
60h D0h
I/O0
Pass
Fail
t
BERS
Address (3 Cycle) Address (3 Cycle)
70h
"0"
"1"
A
12
~ A
17 :
Fixed ’Low’
A
18 :
Fixed ’Low’
A
19
~ A
28 :
Fixed ’Low’
A
12
~ A
17 :
Fixed ’Low’
A
18 :
Fixed ’High’
A
19
~ A
28 :
valid
Two-Plane Block Erase
Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by
three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane.
The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/
Busy status bit (I/O 6).
A
0
~ A
11 :
Valid
A
12
~ A
17 :
Fixed ’Low’
A
18 :
Fixed ’Low’
A
19
~ A
28 :
Fixed ’Low’
A
0
~ A
11 :
Valid
A
12
~ A
17 :
Valid
A
18 :
Fixed ’High’
A
19
~ A
28 :
Valid
2. Any command between 11h and 81h is prohibited except 70h and FFh.
Note*
2