Samsung SC32442B54, User Manual

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K5D2G13ACM-D075
Revision 1.0
December 2006
77
MCP MEMORY
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
CS
RAS
CAS
BA1
A10/AP
CL=3
ADDR
WE
: Don’t care
CLOCK
Page Read Cycle at Different Bank @Burst Length=4
HIGH
RAa CAa
RAa
CL=2
Row Active Read Precharge
Note:
1) CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.
2) To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
BA0
DQ
(A-Bank) (A-Bank) (D-Bank)
{
Note 2)
RCc
Read
(B-Bank)
CBb RDd CCc CDd
RBb RCc RDd
QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
Row Active
(B-Bank)
Row Active
(C-Bank)
Row Active
(D-Bank)
Precharge
(A-Bank)
Read
(C-Bank)
Precharge
(B-Bank)
Read
(D-Bank)
Precharge
(C-Bank)
Note 1)
QAa0
QAa0
RBb
CL=3
CL=2
DQM
{
Hi-Z
Hi-Z