Samsung SC32442B54, User Manual

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K5D2G13ACM-D075
Revision 1.0
December 2006
55
MCP MEMORY
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16
This Mobile SDR SDRAM is organized as four independent
banks of 1,048,576 words x 16 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
: In case x 32
This Mobile SDR SDRAM is organized as four independent
banks of 524,288 words x 32 bits memory arrays. The BA0 ~ BA1
inputs are latched at the time of assertion of RAS and CAS to
select the bank to be used for the operation. The bank addresses
BA0 ~ BA1 are latched at bank active, read, write, mode register
set and precharge operations.
ADDRESS INPUTS (A0 ~ A11)
: In case x 16
The 20 address bits are required to decode the 1,048,576 word
locations are multiplexed into 12 address input pins (A0 ~ A11).
The 12 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 8 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
: In case x 32
The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A0 ~ A10).
The 11 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 8 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16
This Mobile SDR SDRAM is organized as four independent
banks of 2,097,152 words x 16 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
: In case x 32
This Mobile SDR SDRAM is organized as four independent
banks of 1,048,576 words x 32 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
ADDRESS INPUTS (A0 ~ A11)
: In case x 16
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 12 address input pins (A0 ~ A11).
The 12 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
: In case x 32
The 20 address bits are required to decode the 1,048,576 word
locations are multiplexed into 12 address input pins (A0 ~ A11).
The 12 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 8 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
A. DEVICE OPERATIONS
ADDRESSES of 64Mb ADDRESSES of 128Mb