K5D2G13ACM-D075
Revision 1.0
December 2006
14
MCP MEMORY
NAND Flash Technical Notes
Identifying Initial Invalid Block(s)
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)
have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)
does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-
sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on
00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit
/512Byte
ECC.
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-
tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every
initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in
most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the
initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following
suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.
*
Check "FFh" at the column address 2048
Figure 3. Flow chart to create initial invalid block table
Start
Set Block Address = 0
Check "FFh"
Increment Block Address
Last Block ?
End
No
Yes
Yes
Create (or update)
No
Initial
of the 1st and 2nd page in the block
Invalid Block(s) Table
Summary of Contents for SC32442B54
Page 1: ...SC32442B54 USER S MANUAL Revision 1 0 ...
Page 43: ...PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR 1 42 NOTES ...
Page 59: ...PROGRAMMER S MODEL SC32442B RISC MICROPROCESSOR 2 16 NOTES ...
Page 123: ...ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR 3 64 NOTES ...
Page 167: ...THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR 4 44 NOTES ...
Page 187: ...MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR 5 20 NOTES ...
Page 250: ...DMA SC32442B RISC MICROPROCESSOR 8 14 NOTES ...
Page 308: ...PWM TIMER SC32442B RISC MICROPROCESSOR 10 20 NOTES ...
Page 330: ...UART SC32442B RISC MICROPROCESSOR 11 22 NOTES ...
Page 417: ...SC32442B RISC MICROPROCESSOR LCD CONTROLLER 15 45 NOTES ...
Page 427: ...ADC AND TOUCH SCREEN INTERFACE SC32442B RISC MICROPROCESSOR 16 10 NOTES ...
Page 511: ...BUS PRIORITIES SC32442B RISC MICROPROCESSOR 24 2 NOTES ...
Page 562: ...K5D2G13ACM D075 Revision 1 0 December 2006 7 MCP MEMORY 2Gb 256Mb x8 NAND Flash Memory A Die ...
Page 599: ...K5D2G13ACM D075 Revision 1 0 December 2006 44 MCP MEMORY 512Mb 16Mb x32 Mobile SDRAM C Die ...