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SC32442B RISC MICROPROCESSOR

MEMORY CONTROLLER

DEC.13, 2002

5-11

PROGRAMMABLE ACCESS CYCLE

Tcoh

Tcos

Tacs

HCLK

A[24:0]

nGCS

nOE

nWE

nWBE

D[31:0](R)

D[31:0] (W)

Tacc

Tacp

Tcah

Tacs = 1 cycle
Tcos = 1 cycle
Tacc = 3 cycles

Tacp = 2 cycles
Tcoh = 1 cycle
Tcah = 2 cycles

Figure 5-12. SC32442B nGCS Timing Diagram

Summary of Contents for SC32442B54

Page 1: ...SC32442B54 USER S MANUAL Revision 1 0 ...

Page 2: ...viding a complete set of common system peripherals the SC32442B minimizes overall system costs and eliminates the need to configure additional components The integrated on chip functions that are described in this document include Around 500MHz 1 7V arm and 1 2V internal 400MHz 1 4V arm and 1 2V internal 1 8Vmemory 3 3V external I O microprocessor with 16KB I Cache 16KB D Cache MMU External memory...

Page 3: ...wn Supports various types of ROM for booting NOR NAND Flash EEPROM and others NAND Flash Boot Loader Supports booting from NAND flash memory 4KB internal buffer for booting Supports storage memory for NAND flash memory after booting Supports Advanced NAND flash Cache Memory 64 way set associative cache with I Cache 16KB and D Cache 16KB 8words length per line with one valid bit and two dirty bits ...

Page 4: ... bit dual scan 4 bit single scan 8 bit single scan display type Supports monochrome mode 4 gray levels 16 gray levels 256 colors and 4096 colors for STN LCD Supports multiple screen size Typical actual screen size 640x480 320x240 160x160 and others Maximum frame buffer size is 4 Mbytes Maximum virtual screen size in 256 color mode 4096x1024 2048x2048 1024x4096 and others TFT Thin Film Transistor C...

Page 5: ...n 1 1 SD Host Interface Normal Interrupt and DMA data transfer mode byte halfword word transfer DMA burst4 access support only word transfer Compatible with SD Memory Card Protocol version 1 0 Compatible with SDIO Card Protocol version 1 0 64 Bytes FIFO for Tx Rx Compatible with Multimedia Card Protocol version 2 11 SPI Interface Compatible with 2 ch Serial Peripheral Interface Protocol version 2 ...

Page 6: ...Buffer AMBA Bus I F JTAG Data CACHE 16KB WBPA 31 0 DPA 31 0 Bridge DMA 4Ch Clock Generator MPLL A H B B U S Memory CONT SRAM NOR SDRAM BUS CONT Arbitor Decode Power Management Interrupt CONT USB Host CONT ExtMaster LCD DMA LCD CONT A P B B U S I2C GPIO I2S RTC SPI ADC SDI MMC USB Device Watchdog Timer BUS CONT Arbitor Decode Timer PWM 0 3 4 Internal SPI 0 1 UART 0 1 2 NAND Ctrl NAND Flash Boot Loa...

Page 7: ...ROPROCESSOR 1 6 PIN ASSIGNMENTS TOP VIEW A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 V W Y AA AB AC AD AE AF 18 19 20 21 22 23 24 25 26 14mm H x14mm V x1 6mm T Figure 1 2 SC32442B Pin Assignments 332 FBGA ...

Page 8: ...SSOP1 E26 DATA18 A14 ADDR24 GPA9 B23 DATA11 F1 NBE0 A15 DATA2 B24 VDDMOP F2 NGCS7 A16 DATA4 B25 DATA14 F5 VDDI A17 DATA0 B26 DATA13 F6 NGCS0 A18 DATA5 C1 ADDR5 F7 VDDIARM A19 DATA6 C2 NWAIT F8 VDDIARM A20 VDDMOP C25 DATA19 F9 CAMVSYNC GPJ9 A21 DATA7 C26 DATA15 F10 VSSMOP A22 DATA9 D1 ADDR3 F11 CAMCLKOUT GPJ11 A23 DATA10 D2 NGCS4 GPA15 F12 ADDR20 GPA5 A24 DATA16 D25 VSSMOP F13 ADDR19 GPA4 A25 DATA1...

Page 9: ...MOP M21 RXD2 NCTS1 GPH7 R21 SDDAT1 GPE8 H22 NRESET M22 TDO R22 EINT4 GPF4 H25 VSSCOM M25 BATT_FLT R25 RXD0 GPH3 H26 DATA26 M26 DATA29 R26 NRTS0 GPH1 J1 NFWE GPA19 N1 NWE T1 VSS_NF J2 VSSCOM N2 TOUT3 GPB3 T2 VM GPC4 J5 CAMPCLK GPJ8 N5 VDDOP2 T5 VDDIARM J6 CAMDATA3 GPJ3 N6 NXDACK1 GPB7 T6 NXDREQ0 GPB10 J21 NCTS0 GPH0 N12 VSSCOM T21 VDDA_UPLL J22 TOUT2 GPB2 N13 VSSCOM T22 EINT0 GPF0 J25 DATA24 N14 VS...

Page 10: ...26 VCC_NF AB6 VD14 GPD6 NSS1 AE8 VD19 GPD11 Y1 VD5 GPC13 AB7 VD16 GPD8 SPIMOSI1 AE9 VD23 NSS0 GPD15 Y2 VD7 GPC15 AB8 VDDIARM AE10 SDDAT0 GPE7 Y5 VD3 GPC11 AB9 VDDIARM AE11 I2SSDO GPE4 Y6 VCLK GPC1 AB10 SDCLK GPE5 AE12 SDDAT2 GPE9 Y21 NCON0 AB11 SDDAT3 GPE10 AE13 VDDIARM Y22 VDDA_ADC AB12 IICSCL GPE14 AE14 CLKOUT1 GPH10 Y25 VDDA_MPLL AB13 SPIMOSI0 GPE12 AE15 EINT9 GPG1 Y26 VDD_RTC AB14 EINT12 LCD_P...

Page 11: ... A1 NC AF5 VD21 GPD13 A26 NC AF6 VSSQ_SDRAM AF1 NC AF7 VDDQ_SDRAM AF26 NC AF8 CDCLK GPE2 AF9 VSSQ_SDRAM AF10 VDDQ_SDRAM AF11 VSS_SDRAM AF12 VSSQ_SDRAM AF13 VDD_SDRAM AF14 EINT11 NSS1 GPG3 AF15 VDDQ_SDRAM AF16 EINT19 TCLK1 GPG11 AF17 VSSQ_SDRAM AF18 EINT23 NYPON GPG15 AF19 VDDQ_SDRAM AF20 VSSA_ADC AF21 VSSQ_SDRAM AF22 VSSQ_SDRAM AF23 VDDQ_SDRAM AF24 VDD_SDRAM AF25 VSS_SDRAM ...

Page 12: ... ADDR11 ADDR11 Hi z O L O L t12s B12 ADDR12 ADDR12 Hi z O L O L t12s A3 ADDR13 ADDR13 Hi z O L O L t12s A13 ADDR14 ADDR14 Hi z O L O L t12s B13 ADDR15 ADDR15 Hi z O L O L t12s E15 ADDR16 GPA1 ADDR16 Hi z O L O L t12s F14 ADDR17 GPA2 ADDR17 Hi z O L O L t12s B15 ADDR18 GPA3 ADDR18 Hi z O L O L t12s F13 ADDR19 GPA4 ADDR19 Hi z O L O L t12s F12 ADDR20 GPA5 ADDR20 Hi z O L O L t12s B16 ADDR21 GPA6 ADD...

Page 13: ...11 CAMCLKOUT GPJ11 GPJ11 O L I t8 F18 CAMRESET GPJ12 GPJ12 O L I t8 A17 DATA0 DATA0 Hi z Hi z O L I b12s B19 DATA1 DATA1 Hi z Hi z O L I b12s A15 DATA2 DATA2 Hi z Hi z O L I b12s B18 DATA3 DATA3 Hi z Hi z O L I b12s A16 DATA4 DATA4 Hi z Hi z O L I b12s A18 DATA5 DATA5 Hi z Hi z O L I b12s A19 DATA6 DATA6 Hi z Hi z O L I b12s A21 DATA7 DATA7 Hi z Hi z O L I b12s B20 DATA8 DATA8 Hi z Hi z O L I b12s...

Page 14: ...Hi z O L I b12s M26 DATA29 DATA29 Hi z Hi z O L I b12s P26 DATA30 DATA30 Hi z Hi z O L I b12s K25 DATA31 DATA31 Hi z Hi z O L I b12s AB18 DN0 DN0 AI us AB17 DP0 DP0 AI us AA17 DN1 PDN0 DN1 AI us AE17 DP1 PDP0 DP1 AI us T22 EINT0 GPF0 GPF0 Hi z I t8 U26 EINT1 GPF1 GPF1 Hi z I t8 N21 EINT2 GPF2 GPF2 Hi z I t8 T26 EINT3 GPF3 GPF3 Hi z I t8 R22 EINT4 GPF4 GPF4 Hi z I t8 U25 EINT5 GPF5 GPF5 Hi z I t8 K...

Page 15: ...BATT_FLT nBATT_FLT I is F1 nBE0 nBE0 Hi z Hi z O H O H t12s A5 nBE1 nBE1 Hi z Hi z O H O H t12s E1 nBE2 nBE2 Hi z Hi z O H O H t12s B6 nBE3 nBE3 Hi z Hi z O H O H t12s Y21 NCON NCON I is L1 FRnB FRnB Hi z O L I d2s J1 nFWE GPA19 nFWE O H Hi z O H O H t12s K1 nFRE GPA20 nFRE O H Hi z O H O H t12s G5 nFCE GPA22 nFCE O H Hi z O H O H t12s H2 CLE GPA17 CLE O L Hi z O L O L t12s H1 ALE GPA18 ALE O L Hi...

Page 16: ...2 GPB2 O L I t8 N2 TOUT3 GPB3 GPB3 O L I t8 P2 TCLK0 GPB4 GPB4 I t8 M6 nXBACK GPB5 GPB5 O H I t8 P5 nXBREQ GPB6 GPB6 I t8 N6 nXDACK1 GPB7 GPB7 O H I t8 P6 nXDREQ1 GPB8 GPB8 I t8 R2 nXDACK0 GPB9 GPB9 O H I t8 T6 nXDREQ0 GPB10 GPB10 I t8 AE23 OM0 OM0 I is AB22 OM1 OM1 I is AA22 OM2 OM2 I is AE19 OM3 OM3 I is F20 PWREN PWREN O H O L O H b8 J21 nCTS0 GPH0 GPH0 I t8 R26 nRTS0 GPH1 GPH1 O H I t8 L22 TXD...

Page 17: ...DCMD GPE6 GPE6 Hi z I t8 AE10 SDDAT0 GPE7 GPE7 Hi z I t8 R21 SDDAT1 GPE8 GPE8 Hi z I t8 AE12 SDDAT2 GPE9 GPE9 Hi z I t8 AB11 SDDAT3 GPE10 GPE10 Hi z I t8 AA15 SPIMISO0 GPE11 GPE11 Hi z I t8 AB13 SPIMOSI0 GPE12 GPE12 Hi z I t8 AA16 SPICLK0 GPE13 GPE13 Hi z I t8 AB12 IICSCL GPE14 GPE14 Hi z I d8 U21 IICSDA GPE15 GPE15 Hi z I d8 E20 TCK TCK I I is F22 TDI TDI I I is M22 TDO TDO O O O ot E21 TMS TMS I...

Page 18: ... I t8 AE1 VD13 GPD5 GPD5 O L O I t8 AB6 VD14 GPD6 GPD6 O L O I t8 AE6 VD15 GPD7 GPD7 O L O I t8 AB7 VD16 SPIMISO1 GPD8 GPD8 O L Hi z I t8 AE4 VD17 SPIMOSI1 GPD9 GPD9 O L Hi z I t8 AE3 VD18 SPICLK1 GPD10 GPD10 O L Hi z I t8 AE8 VD19 GPD11 GPD11 O L Hi z I t8 AF4 VD20 GPD12 GPD12 O L Hi z I t8 AF5 VD21 GPD13 GPD13 O L Hi z I t8 AE7 VD22 nSS1 GPD14 GPD14 O L Hi z I t8 AE9 VD23 nSS0 GPD15 GPD15 O L Hi...

Page 19: ...arm VDDiarm P P P d12c U5 VDDiarm VDDiarm P P P d12c AD2 VDDiarm VDDiarm P P P d12c AB8 VDDiarm VDDiarm P P P d12c AB9 VDDiarm VDDiarm P P P d12c AE13 VDDiarm VDDiarm P P P d12c AA5 VDDiarm VDDiarm P P P d12c G2 VDDMOP VDDMOP P P P d18o H21 VDDMOP VDDMOP P P P d18o B24 VDDMOP VDDMOP P P P d18o A20 VDDMOP VDDMOP P P P d18o E17 VDDMOP VDDMOP P P P d18o E12 VDDMOP VDDMOP P P P d18o E8 VDDMOP VDDMOP P...

Page 20: ...NF P P P AF20 VSSA_ADC VSSA_ADC P P P Sth AB26 VSSA_MPLL VSSA_MPLL P P P st P22 VSSA_UPLL VSSA_UPLL P P P st J2 VSSCOM VSSCOM P P P si M5 VSSCOM VSSCOM P P P si R1 VSSCOM VSSCOM P P P si W2 VSSCOM VSSCOM P P P si AB2 VSSCOM VSSCOM P P P si M14 VSSCOM VSSCOM P P P si K22 VSSCOM VSSCOM P P P si H25 VSSCOM VSSCOM P P P si M13 VSSCOM VSSCOM P P P si N12 VSSCOM VSSCOM P P P si N13 VSSCOM VSSCOM P P P s...

Page 21: ... P s18 F10 VSSMOP VSSMOP P P P s18 U22 VSSOP VSSOP P P P so AA21 VSSOP VSSOP P P P so B22 VSSOP1 VSSOP1 P P P so H6 VSSOP2 VSSOP2 P P P so W1 VSSOP3 VSSOP3 P P P so AA7 VSSOP3 VSSOP3 P P P so AD1 VSS_SDRAM VSS_SDRAM P P P so AD26 VSS_SDRAM VSS_SDRAM P P P so AE2 VSS_SDRAM VSS_SDRAM P P P so AF11 VSS_SDRAM VSS_SDRAM P P P so AF25 VSS_SDRAM VSS_SDRAM P P P so AF6 VSSQ_SDRAM VSSQ_SDRAM P P P so AF9 V...

Page 22: ...2 mark indicates the unchanged pin state at Bus Request mode 3 Hi z or Pre means Hi z or early state and it is determined by the setting of MISCCR register 4 AI AO means analog input analog output 5 P I and O mean power input and output respectively 6 The I O state nRESET shows the pin status in the nRESET duration below nRESET FCLK nRESET 4 OSCin ...

Page 23: ...onal pad LVCMOS schmitt trigger 100Kohm pull down resistor with control tri state Io 12mA is phis Input pad LVCMOS schmitt trigger level us pbusb0 USB pad ot phot8 Output pad tri state Io 8mA b8 phob8 Output pad Io 8mA r10 phiar10_abb Analog input pad with 10 ohm resistor ia phia_abb Analog input pad m26 phsoscm26 Oscillator cell with enable and feedback resistor d8 phbsd8sm Bi directional pad LVC...

Page 24: ...hat the current bus cycle is a write cycle nOE O nOE Output Enable indicates that the current bus cycle is a read cycle nXBREQ I nXBREQ Bus Hold Request allows another bus master to request control of the local bus BACK active indicates that bus control has been granted nXBACK O nXBACK Bus Hold Acknowledge indicates that the SC32442B has surrendered control of the local bus to another bus master n...

Page 25: ...ctronics Company TFT LCD panel control signal LCD_HCLK O SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal TP O SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal STH O SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal LCD_LPCOE O SEC TFT Timing control signal for specific TFT LCD LCD_LPCREV O SEC TFT Timing control signal for specific TFT LC...

Page 26: ... IICSCL IO IIC bus clock IIS Bus I2SLRCK IO IIS bus channel select clock I2SSDO O IIS bus serial data output I2SSDI I IIS bus serial data input I2SSCLK IO IIS bus serial clock CDCLK O CODEC system clock Touch Screen nXPON O Plus X axis on off control signal XMON O Minus X axis on off control signal nYPON O Plus Y axis on off control signal YMON O Minus Y axis on off control signal USB Host DN 1 0 ...

Page 27: ...ts some ports are output only TIMMER PWM TOUT 3 0 O Timer output 3 0 TCLK 1 0 I External timer clock input JTAG TEST LOGIC nTRST I nTRST TAP Controller Reset resets the TAP controller at start If debugger is used A 10K pull up resistor has to be connected If debugger black ICE is not used nTRST pin must be issued by a low active pulse Typically connected to nRESET TMS I TMS TAP Controller Mode Sel...

Page 28: ... the processor power has been stabilized nRSTOUT O For external device reset control nRSTOUT nRESET nWDTRST SW_RESET PWREN O 1 2V 1 3V core power on off control signal nBATT_FLT I Probe for battery state Does not wake up at Sleep mode in case of low battery state If it isn t used it has to be High VDDOP OM 3 2 I OM 3 2 determines how the clock is made OM 3 2 00b Crystal is used for MPLL CLK source...

Page 29: ...nd digital VDD VSSA_UPLL P SC32442B UPLL analog and digital VSS VDDA_ADC P SC32442B ADC VDD 3 3V VSSA_ADC P SC32442B ADC VSS VCC_NF P NAND VDD in SC32442B VSS_NF P NAND VSS in SC32442B VDD_SDRAM P mSDRAM VDD Core in SC32442B VSS_SDRAM P mSDRAM VSS Core in SC32442B VDDQ_SDRAM P mSDRAM VDD IO in SC32442B VSSQ_SDRAM P mSDRAM VSS IO in SC32442B CS O mSDRAM chip select in SC32442B This pin should be co...

Page 30: ...Control BANKCON0 0x48000004 Boot ROM Control BANKCON1 0x48000008 BANK1 Control BANKCON2 0x4800000C BANK2 Control BANKCON3 0x48000010 BANK3 Control BANKCON4 0x48000014 BANK4 Control BANKCON5 0x48000018 BANK5 Control BANKCON6 0x4800001C BANK6 Control BANKCON7 0x48000020 BANK7 Control REFRESH 0x48000024 DRAM SDRAM Refresh Control BANKSIZE 0x48000028 Flexible Bank Size MRSRB6 0x4800002C Mode register ...

Page 31: ...28 HcBulkCurrentED 0x4900002C HcDoneHead 0x49000030 HcRmInterval 0x49000034 Frame Counter Group HcFmRemaining 0x49000038 HcFmNumber 0x4900003C HcPeriodicStart 0x49000040 HcLSThreshold 0x49000044 HcRhDescriptorA 0x49000048 Root Hub Group HcRhDescriptorB 0x4900004C HcRhStatus 0x49000050 HcRhPortStatus1 0x49000054 HcRhPortStatus2 0x49000058 Interrupt Controller SRCPND 0X4A000000 W R W Interrupt Reque...

Page 32: ...l DCON1 0x4B000050 DMA 1 Control DSTAT1 0x4B000054 R DMA 1 Count DCSRC1 0x4B000058 DMA 1 Current Source DCDST1 0x4B00005C DMA 1 Current Destination DMASKTRIG1 0x4B000060 R W DMA 1 Mask Trigger DISRC2 0x4B000080 DMA 2 Initial Source DISRCC2 0x4B000084 DMA 2 Initial Source Control DIDST2 0x4B000088 DMA 2 Initial Destination DIDSTC2 0x4B00008C DMA 2 Initial Destination Control DCON2 0x4B000090 DMA 2 ...

Page 33: ... 0X4D000000 W R W LCD Control 1 LCDCON2 0X4D000004 LCD Control 2 LCDCON3 0X4D000008 LCD Control 3 LCDCON4 0X4D00000C LCD Control 4 LCDCON5 0X4D000010 LCD Control 5 LCDSADDR1 0X4D000014 STN TFT Frame Buffer Start Address1 LCDSADDR2 0X4D000018 STN TFT Frame Buffer Start Address2 LCDSADDR3 0X4D00001C STN TFT Virtual Screen Address Set REDLUT 0X4D000020 STN Red Lookup Table GREENLUT 0X4D000024 STN Gre...

Page 34: ...0 NAND Flash Data NFMECC0 0x4E000014 NAND Flash Main area ECC0 1 NFMECC1 0x4E000018 NAND Flash Main area ECC2 3 NFSECC 0x4E00001C NAND Flash Spare area ECC NFSTAT 0x4E000020 NAND Flash Operation Status NFESTAT0 0x4E000024 NAND Flash ECC Status for I O 7 0 NFESTAT1 0x4E000028 NAND Flash ECC Status for I O 15 8 NFMECC0 0x4E00002C R NAND Flash Main area ECC0 status NFMECC1 0x4E000030 NAND Flash Main ...

Page 35: ...A3 0x4F000040 Cr 3rd frame start address for codec DMA CICOCRSA4 0x4F000044 Cr 4th frame start address for codec DMA CICOTRGFMT 0x4F000048 Target image format of codec DMA CICOCTRL 0x4F00004C Codec DMA control related CICOSCPRERATIO 0x4F000050 Codec pre scaler ratio control CICOSCPREDST 0x4F000054 Codec pre scaler destination format CICOSCCTRL 0x4F000058 Codec main scaler control CICOTAREA 0x4F000...

Page 36: ... ULCON1 0x50004000 UART 1 Line Control UCON1 0x50004004 UART 1 Control UFCON1 0x50004008 UART 1 FIFO Control UMCON1 0x5000400C UART 1 Modem Control UTRSTAT1 0x50004010 R UART 1 Tx Rx Status UERSTAT1 0x50004014 UART 1 Rx Error Status UFSTAT1 0x50004018 UART 1 FIFO Status UMSTAT1 0x5000401C UART 1 Modem Status UTXH1 0x50004023 0x50004020 B W UART 1 Transmission Hold URXH1 0x50004027 0x50004024 R UAR...

Page 37: ...0010 Timer Compare Buffer 0 TCNTO0 0x51000014 R Timer Count Observation 0 TCNTB1 0x51000018 R W Timer Count Buffer 1 TCMPB1 0x5100001C Timer Compare Buffer 1 TCNTO1 0x51000020 R Timer Count Observation 1 TCNTB2 0x51000024 R W Timer Count Buffer 2 TCMPB2 0x51000028 Timer Compare Buffer 2 TCNTO2 0x5100002C R Timer Count Observation 2 TCNTB3 0x51000030 R W Timer Count Buffer 3 TCMPB3 0x51000034 Timer...

Page 38: ... Endpoint Control Status IN_CSR2_REG 0x5200018B 0x52000188 In Endpoint Control Status MAXP_REG 0x52000183 0x52000180 Endpoint Max Packet OUT_CSR1_REG 0x52000193 0x52000190 Out Endpoint Control Status OUT_CSR2_REG 0x52000197 0x52000194 Out Endpoint Control Status OUT_FIFO_CNT1_REG 0x5200019B 0x52000198 R Endpoint Out Write Count OUT_FIFO_CNT2_REG 0x5200019F 0x5200019C Endpoint Out Write Count EP0_F...

Page 39: ...0x52000253 0x52000250 EP3 DMA Total Tx Counter EP3_DMA_TTC_H 0x52000257 0x52000254 EP3 DMA Total Tx Counter EP4_DMA_CON 0x5200025B 0x52000258 EP4 DMA Interface Control EP4_DMA_UNIT 0x5200025F 0x5200025C EP4 DMA Tx Unit Counter EP4_DMA_FIFO 0x52000263 0x52000260 EP4 DMA Tx FIFO Counter EP4_DMA_TTC_L 0x52000267 0x52000264 EP4 DMA Total Tx Counter EP4_DMA_TTC_M 0x5200026B 0x52000268 EP4 DMA Total Tx ...

Page 40: ...ntrol D GPECON 0x56000040 Port E Control GPEDAT 0x56000044 Port E Data GPEDN 0x56000048 Pull down Control E GPFCON 0x56000050 Port F Control GPFDAT 0x56000054 Port F Data GPFDN 0x56000058 Pull down Control F GPGCON 0x56000060 Port G Control GPGDAT 0x56000064 Port G Data GPGDN 0x56000068 Pull down Control G GPHCON 0x56000070 Port H Control GPHDAT 0x56000074 Port H Data GPHDN 0x56000078 Pull down Co...

Page 41: ...m Register GSTATUS4 0x560000BC Inform Register MSLCON 0x560000CC Memory Sleep Control Register RTC RTCCON 0x57000043 0x57000040 B R W RTC Control TICNT 0x57000047 0x57000044 Tick time count RTCALM 0x57000053 0x57000050 RTC Alarm Control ALMSEC 0x57000057 0x57000054 Alarm Second ALMMIN 0x5700005B 0x57000058 Alarm Minute ALMHOUR 0x5700005F 0x5700005C Alarm Hour ALMDATE 0x57000063 0x57000060 Alarm Da...

Page 42: ...PPRE0 1 0x5900000C 2C SPI Baud Rate Prescaler SPTDAT0 1 0x59000010 30 SPI Tx Data SPRDAT0 1 0x59000014 34 R SPI Rx Data SD interface SDICON 0x5A000000 W R W SDI Control SDIPRE 0x5A000004 SDI Baud Rate Prescaler SDICARG 0x5A000008 SDI Command Argument SDICCON 0x5A00000C SDI Command Control SDICSTA 0x5A000010 R C SDI Command Status SDIRSP0 0x5A000014 R SDI Response SDIRSP1 0x5A000018 SDI Response SD...

Page 43: ...PRODUCT OVERVIEW SC32442B RISC MICROPROCESSOR 1 42 NOTES ...

Page 44: ...e achieved by executing a BX instruction with the state bit bit 0 set in the operand register Transition to THUMB state will also occur automatically on return from an exception IRQ FIQ UNDEF ABORT SWI etc if the exception is entered with the processor in THUMB state Entering ARM State Entry into ARM state can be done by the following methods On execution of the BX instruction with the state bit c...

Page 45: ...IAN FORMAT In Little Endian format the lowest numbered byte in a word is considered the word s least significant byte and the highest numbered byte the most significant Byte 0 of the memory system is therefore connected to data lines 7 through 0 31 23 8 7 0 4 0 8 Higher Address Lower Address Word Address Least significant byte is at lowest address Word is addressed by byte address of least signifi...

Page 46: ...igure 2 3 shows which register is available in each mode the banked registers are marked with a shaded triangle The ARM state register set contains 16 directly accessible registers R0 to R15 All of these except R15 are general purpose and may be used to hold either data or address values In addition to these there is a seventeenth register used to store status information Register 14 This register...

Page 47: ...R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13_abt R14_abt R15 PC R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13_irq R14_irq R15 PC R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13_und R14_und R15 PC System User FIQ Supervisor IRQ Abort Undefined ARM State General Registers and Program Counter ARM State Program Status Registers CPSR CPSR SPSR_fiq CPSR SPSR_irq banked register CPSR SPSR_und CPSR SPSR_ab...

Page 48: ...egisters SPSRs for each privileged mode This is shown in Figure 2 4 R0 R1 R2 R3 R4 R5 R6 R7 LR SP PC System User FIQ Supervisor IRQ Abort Undefined THUMB State General Registers and Program Counter THUMB State Program Status Registers CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und banked register LR_fiq R0 R1 R2 R3 R4 R5 R6 R7 SP_fiq PC LR_svc R0 R1 R2 R3 R4 R5 R6 R7 SP...

Page 49: ...B state SP maps onto ARM state R13 THUMB state LR maps onto ARM state R14 The THUMB state Program Counter maps onto the ARM state Program Counter R15 This relationship is shown in Figure 2 5 R0 R1 R2 R3 R4 R5 R6 R7 Stack Pointer SP Link register LR Program Counter PC CPSR SPSR R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 Stack Pointer R13 Link register R14 Program Counter R15 CPSR SPSR Lo registers H...

Page 50: ...er values with the CMP and ADD instructions For more information Please refer to Figure 3 34 THE PROGRAM STATUS REGISTERS The ARM920T contains a Current Program Status Register CPSR plus five Saved Program Status Registers SPSRs for use by exception handlers These register s functions are Hold information about the most recently performed ALU operation Control the enabling and disabling of interru...

Page 51: ...ecuting in ARM state This is reflected on the TBIT external signal Note that the software must never change the state of the TBIT in the CPSR If this happens the processor will enter an unpredictable state Interrupt disable bits I and F bits are the interrupt disable bits When set these disable the IRQ and FIQ interrupts respectively The mode bits The M4 M3 M2 M1 and M0 bits M 4 0 are the mode bit...

Page 52: ...sor R7 R0 LR_svc SP_svc PC CPSR SPSR_svc R12 R0 R14_svc R13_svc PC CPSR SPSR_svc 10111 Abort R7 R0 LR_abt SP_abt PC CPSR SPSR_abt R12 R0 R14_abt R13_abt PC CPSR SPSR_abt 11011 Undefined R7 R0 LR_und SP_und PC CPSR SPSR_und R12 R0 R14_und R13_und PC CPSR 11111 System R7 R0 LR SP PC CPSR R14 R0 PC CPSR Reserved bits The remaining bits in the PSR s are reserved While changing a PSR s flag or control ...

Page 53: ...rogram resumes from the correct place on return from the exception This means that the exception handler need not determine which state the exception was entered from For example in the case of SWI MOVS PC R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state 2 Copies the CPSR into the appropriate SPSR 3 Forces the CPSR mode bits to a v...

Page 54: ... which generated the data abort 4 The value saved in R14_svc upon reset is unpredictable FIQ The FIQ Fast Interrupt Request exception is designed to support a data transfer or channel process and in ARM state has sufficient private registers to remove the need for register saving thus minimizing the overhead of context switching FIQ is externally generated by taking the nFIQ input LOW This input c...

Page 55: ... Single data transfer instructions LDR STR write back modified base registers the Abort handler must be aware of this The swap instruction SWP is aborted as though it had not been executed Block data transfer instructions LDM STM complete If write back is set the base is updated If the instruction would have overwritten the base with data ie it has the base in the transfer list the overwriting is ...

Page 56: ... handled it takes the undefined instruction trap This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation After emulating the failed instruction the trap handler should execute the following irrespective of the state ARM or Thumb MOVS PC R14_und This restores the CPSR and returns to the instruction following the undefined instruction Exception Vectors The ...

Page 57: ...rupt are mutually exclusive since they each correspond to particular non overlapping decodings of the current instruction If a data abort occurs at the same time as a FIQ and FIQs are enabled ie the CPSR s F flag is clear ARM920T enters the data abort handler and then immediately proceeds to the FIQ vector A normal return from FIQ will cause the data abort handler to resume execution Placing data ...

Page 58: ... uses a continuous 20 MHz processor clock The maximum IRQ latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchronizer Tsyncmin plus Tfiq This is 4 processor cycles RESET When th...

Page 59: ...PROGRAMMER S MODEL SC32442B RISC MICROPROCESSOR 2 16 NOTES ...

Page 60: ...CP CP CP CRm CRm Ignored by processor 0 1 Offset Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond 0 0 0 0 0 0 A S A S U 1 0 0 0 0 0 0 0 0 0 0 1 B 1 0 0 0 1 0 0 0 1 1 1 1 1 1 0 0 0 0 H H 0 0 0 0 S S 1 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 Multiply Multiply Long Single Data Swap Branch and Exchange Halfword Data Transfer register offset Halfword Data Transfer immendiate offset Sin...

Page 61: ...rry ADD Add Rd Rn Op2 AND AND Rd Rn AND Op2 B Branch R15 address BIC Bit Clear Rd Rn AND NOT Op2 BL Branch with Link R14 R15 R15 address BX Branch and Exchange R15 Rn T bit Rn 0 CDP Coprocessor Data Processing Coprocessor specific CMN Compare Negative CPSR flags Rn Op2 CMP Compare CPSR flags Rn Op2 EOR Exclusive OR Rd Rn AND NOT Op2 OR Op2 AND NOT Rn LDC Load coprocessor from memory Coprocessor lo...

Page 62: ...N Move negative register Rd 0 FFFFFFFF EOR Op2 ORR OR Rd Rn OR Op2 RSB Reverse Subtract Rd Op2 Rn RSC Reverse Subtract with Carry Rd Op2 Rn 1 Carry SBC Subtract with Carry Rd Rn Op2 1 Carry STC Store coprocessor register to memory address CRn STM Store Multiple Stack manipulation Push STR Store register to memory address Rd SUB Subtract Rd Rn Op2 SWI Software Interrupt OS call SWP Swap register wi...

Page 63: ...f the Z flag is set In practice fifteen different conditions may be used these are listed in Table 3 2 The sixteenth 1111 is reserved and must not be used In the absence of a suffix the condition field for most instructions is set to Always suffix AL This means the instruction will always be executed regardless of the CPSR condition codes Table 3 2 Condition Code Summary Code Suffix Flags Meaning ...

Page 64: ...s ARM or THUMB instructions 31 24 27 19 15 8 7 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Cond Rn 28 16 11 12 23 20 4 3 3 0 Operand Register If bit0 of Rn 1 subsequent instructions decoded as THUMB instructions If bit0 of Rn 0 subsequent instructions decoded as ARM instructions 31 28 Condition Field Figure 3 2 Branch and Exchange Instructions INSTRUCTION CYCLE TIMES The BX instruction takes...

Page 65: ...B state BX R0 Branch and change to THUMB state CODE16 Assemble subsequent code as Into_THUMB THUMB instructions ADR R5 Back_to_ARM Generate branch target to word aligned address hence bit 0 is low and so change back to ARM state BX R5 Branch and change back to ARM state ALIGN Word alignment CODE32 Assemble subsequent code as ARM instructions Back_to_ARM ...

Page 66: ...nstruction Branches beyond 32Mbytes must use an offset or absolute destination which has been previously loaded into a register In this case the PC should be manually saved in R14 if a Branch with Link type operation is required THE LINK BIT Branch with Link BL writes the old PC into the link register R14 of the current bank The PC value written into R14 is adjusted to allow for the prefetch and c...

Page 67: ...Lways will be used expression The destination The assembler calculates the offset Examples here BAL here Assembles to 0xEAFFFFFE note effect of PC offset B there Always condition used as default CMP R1 0 Compare R1 with zero and branch to fred if R1 was zero otherwise continue BEQ fred Continue to next instruction BL sub ROM Call subroutine at computed address ADDS R1 1 Add 1 to register 1 setting...

Page 68: ...10 SUB Rd Op1 Op2 0011 RSB Rd Op2 Op1 0100 ADD Rd Op1 Op2 0101 ADC Rd Op1 Op2 C 0110 SBC Rd OP1 Op2 C 1 0111 RSC Rd Op2 Op1 C 1 1000 TST set condition codes on Op1 AND Op2 1001 TEO set condition codes on OP1 EOR Op2 1010 CMP set condition codes on Op1 Op2 1011 SMN set condition codes on Op1 Op2 1100 ORR Rd Op1 OR Op2 1101 MOV Rd Op2 1110 BIC Rd Op1 AND NOT Op2 1111 MVN Rd NOT Op2 25 Immediate oper...

Page 69: ...tated 8 bit immediate value Imm according to the value of the I bit in the instruction The condition codes in the CPSR may be preserved or updated as a result of this instruction according to the value of the S bit in the instruction Certain operations TST TEQ CMP CMN do not write the result to Rd They are used only to perform tests and to set the condition codes on the result and always have the ...

Page 70: ...ry SBC 0110 Operand1 operand2 carry 1 RSC 0111 Operand2 operand1 carry 1 TST 1000 As AND but result is not written TEQ 1001 As EOR but result is not written CMP 1010 As SUB but result is not written CMN 1011 As ADD but result is not written ORR 1100 Operand1 OR operand2 MOV 1101 Operand2 operand1 is ignored BIC 1110 Operand1 AND NOT operand2 Bit clear MVN 1111 NOT operand2 operand1 is ignored The ...

Page 71: ...Operations Instruction specified shift amount When the shift amount is specified in the instruction it is contained in a 5 bit field which can take any value from 0 to 31 A Logical Shift Left LSL takes the contents of Rm and moves each bit by the specified amount to a more significant position The least significant bits of the result are filled with zeros and the high bits of Rm which do not map i...

Page 72: ...OR 0 into LSL 0 and allow LSR 32 to be specified An Arithmetic Shift Right ASR is similar to logical shift right except that the high bits are filled with bit 31 of Rm instead of zeros This preserves the sign in 2 s complement notation For example ASR 5 is shown in Figure 3 8 31 Contents of Rm Value of Operand 2 0 carry out 4 5 30 Figure 3 8 Arithmetic Shift Right The form of the shift field which...

Page 73: ...n Figure 3 9 31 Contents of Rm Value of Operand 2 0 carry out 4 5 Figure 3 9 Rotate Right The form of the shift field which might be expected to give ROR 0 is used to encode a special function of the barrel shifter rotate right extended RRX This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as show...

Page 74: ...sult will be a logical extension of the shift described above 1 LSL by 32 has result zero carry out equal to bit 0 of Rm 2 LSL by more than 32 has result zero carry out zero 3 LSR by 32 has result zero carry out equal to bit 31 of Rm 4 LSR by more than 32 has result zero carry out zero 5 ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm 6 ROR by 32 has result equal to Rm...

Page 75: ...r is used directly The PC value will be the address of the instruction plus 8 or 12 bytes due to instruction prefetching If the shift amount is specified in the instruction the PC will be 8 bytes ahead If a register is used to specify the shift amount the PC will be 12 bytes ahead TEQ TST CMP AND CMN OPCODES NOTES TEQ TST CMP and CMN do not write the result of their operation but do set flags in t...

Page 76: ...assembler will attempt to generate a shifted immediate 8 bit field to match the expression If this is impossible it will give an error shift Shiftname register or shiftname expression or RRX rotate right one bit with extend shiftname s ASL LSL LSR ASR ROR ASL is a synonym for LSL they assemble to the same code EXAMPLES ADDEQ R2 R4 R5 If the Z flag is set make R2 R4 R5 TEQS R4 3 Test R4 for equalit...

Page 77: ...egister contents to be transferred to the condition code flags N Z C and V of CPSR or SPSR_ mode without affecting the control bits In this case the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR OPERAND RESTRICTIONS In user mode the control bits of the CPSR are protected from change so only the condition code flags o...

Page 78: ... MRS transfer PSR contents to a register 0 3 0 Source Register 22 Destination PSR 0 CPSR 1 SPSR_ current mode 31 28 Condition Field 15 12 Destination Register 22 Source PSR 0 CPSR 1 SPSR_ current mode 31 28 Condition Field 3 0 Source Register 11 4 Source operand is an immediate value 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 22 Destination PSR 0 CPSR 1 SPSR_ current mode 25 Imme...

Page 79: ... appropriate PSR register to a general register using the MRS instruction changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction EXAMPLES The following sequence performs a mode change MRS R0 CPSR Take a copy of the CPSR BIC R0 R0 0x1F Clear the mode bits ORR R0 R0 new_mode Select new mode MSR CPSR R0 Write back the modified CPSR ...

Page 80: ...ther than R15 psr CPSR CPSR_all SPSR or SPSR_all CPSR and CPSR_all are synonyms as are SPSR and SPSR_all psrf CPSR_flg or SPSR_flg expression Where this is used the assembler will attempt to generate a shifted immediate 8 bit field to match the expression If this is impossible it will give an error EXAMPLES In User mode the instructions behave as follows MSR CPSR_all Rm CPSR 31 28 Rm 31 28 MSR CPS...

Page 81: ...0 8 7 4 3 0 Figure 3 12 Multiply Instructions The multiply form of the instruction gives Rd Rm Rs Rn is ignored and should be set to zero for compatibility with possible future upgrades to the instruction set The multiply accumulate form gives Rd Rm Rs Rn which can save an explicit ADD instruction in some circumstances Both forms of the instruction work on operands which may be considered as signe...

Page 82: ...ned Operand A has the value 4294967286 operand B has the value 20 and the result is 85899345720 which is represented as 0x13FFFFFF38 so the least significant 32 bits are 0xFFFFFF38 Operand Restrictions The destination register Rd must not be the same as the operand register Rm R15 must not be used as an operand or as the destination register All other register combinations will give correct result...

Page 83: ...ively m The number of 8 bit multiplier array cycles is required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows 1 If bits 32 8 of the multiplier operand are all zero or all one 2 If bits 32 16 of the multiplier operand are all zero or all one 3 If bits 32 24 of the multiplier operand are all zero or all one 4 In...

Page 84: ...0 1 Rs Rm A 8 7 4 3 0 Figure 3 13 Multiply Long Instructions The multiply forms UMULL and SMULL take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi RdLo Rm Rs The lower 32 bits of the 64 bit result are written to RdLo the upper 32 bits of the result are written to RdHi The multiply accumulate forms UMLAL and SMLAL take two 32 bit numbers multiply them and add a 64...

Page 85: ...cles to execute where m is the number of 8 bit multiplier array cycles required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows For Signed INSTRUCTIONS SMULL SMLAL If bits 31 8 of the multiplier operand are all zero or all one If bits 31 16 of the multiplier operand are all zero or all one If bits 31 24 of the m...

Page 86: ...ltiply Accumulate Long 32 x 32 64 64 SMULL cond S RdLo RdHi Rm Rs Signed Multiply Long 32 x 32 64 SMLAL cond S RdLo RdHi Rm Rs Signed Multiply Accumulate Long 32 x 32 64 64 where cond Two character condition mnemonic See Table 3 2 S Set condition codes if S present RdLo RdHi Rm Rs Expressions evaluating to a register number other than R15 EXAMPLES UMULL R1 R4 R2 R3 R4 R1 R2 R3 UMLALS R1 R5 R2 R3 R...

Page 87: ...xing is required 31 27 19 15 0 Cond 28 16 11 12 21 23 B 20 L Rn Rd 22 01 I P U Offset W 26 24 25 15 12 Source Destination Registers 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Byte Word Bit 0 Transfer word quantity 1 Transfer byte quantity 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to...

Page 88: ... class See Figure 3 5 BYTES AND WORDS This instruction class may be used to transfer a byte B 1 or a word B 0 between an ARM920T register and memory The action of LDR B and STR B instructions is influenced by the BIGEND control signal of ARM920T core The two possible configurations are described below Little Endian Configuration A byte load LDRB expects the data on data bus inputs 7 through 0 if t...

Page 89: ...imes across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR should generate a word aligned address An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24 This means that half words accessed at these offsets wi...

Page 90: ...t to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value EXAMPLE LDR R0 R1 R1 Therefore a post indexed LDR or STR where Rm is the same register as Rn should not be used DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a system which uses virtual m...

Page 91: ...T pipelining In this case base write back should not be specified Address can be 1 An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 ...

Page 92: ...ss to R2 STR R1 R2 R4 Store R1 at R2 and write back R2 R4 to R2 LDR R1 R2 16 Load R1 from contents of R2 16 but don t write back LDR R1 R2 R3 LSL 2 Load R1 from contents of R2 R3 4 LDREQB R1 R6 5 Conditionally load byte at R6 5 into R1 bits 0 to 7 filling bits 8 to 31 with zeros STR R1 PLACE Generate PC relative offset to address PLACE PLACE ...

Page 93: ...t of this calculation may be written back into the base register if auto indexing is required 31 27 19 15 Cond 28 16 11 12 21 23 0 20 L Rn Rd 3 0 Offset Register 6 5 S H 0 0 SWP instruction 0 1 Unsigned halfword 1 1 Signed byte 1 1 Signed halfword 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write back 0 No write back 1 Write address i...

Page 94: ...rom the base may be either a 8 bit unsigned binary immediate value in the instruction or a second register The 8 bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word such that bit 11 becomes the MSB and bit 0 becomes the LSB The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre ind...

Page 95: ...nfiguration A signed byte load LDRSB expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary on data bus inputs 15 through to 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 2 A h...

Page 96: ... through to 0 The external memory system should activate the appropriate halfword subsystem to store the data Note Please note that the address must be halfword aligned if bit 0 of the address is HIGH this will cause unpredictable behavior USE OF R15 Write back should not be specified if R15 is specified as the base register Rn While using R15 as the base register you must remember it contains add...

Page 97: ...ase and a corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn expression offset of expression bytes Rn Rm offset of contents of index register 3 A post indexed addressing specification Rn expression ...

Page 98: ...3 R4 14 Store the halfword in R3 at R14 14 but don t write back LDRSB R8 R2 223 Load R8 with the sign extended contents of the byte address contained in R2 and write back R2 223 to R2 LDRNESH R11 R0 Conditionally load R11 with the sign extended contents of the halfword address contained in R0 HERE Generate PC relative offset to address FRED STRH R5 PC FRED HERE 8 Store the halfword in R5 at addres...

Page 99: ...t field in the instruction with each bit corresponding to a register A 1 in bit 0 of the register field will cause R0 to be transferred a 0 will cause it not to be transferred similarly bit 1 controls the transfer of R1 and so on Any subset of the registers or all the registers may be specified The only restriction is that the register list should not be empty Whenever R15 is stored to memory the ...

Page 100: ...nsfers the addresses used and the value of Rn after the instruction has completed In all cases had write back of the modified base not been required W 0 Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction when it would have been overwritten with the loaded value Please check the meaning again ADDRESS ALIGNMENT The addre...

Page 101: ... R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3 20 Pre Increment Addressing Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3 21 Post Decrement Addressing ...

Page 102: ... Transfer The registers transferred are taken from the User bank rather than the bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed R15 not in List and S Bit Set User Bank Transfer For both LDM and STM instructions the User bank registers are transferred rather than the register bank...

Page 103: ...change to the internal state of the processor will be the modification of the base register if write back was specified and this must be reversed by software and the cause of the abort resolved before the instruction may be retried Aborts during LDM Instructions When ARM920T detects a data abort during a load multiple instruction it modifies the operation of the instruction to ensure that recovery...

Page 104: ... instruction are shown in the following table 3 6 Table 3 6 Addressing Mode Names Name Stack Other L bit P bit U bit Pre Increment Load LDMED LDMIB 1 1 1 Post Increment Load LDMFD LDMIA 1 0 1 Pre Decrement Load LDMEA LDMDB 1 1 0 Post Decrement Load LDMFA LDMDA 1 0 0 Pre Increment Store STMFA STMIB 0 1 1 Post Increment Store STMEA STMIA 0 0 1 Pre Decrement Store STMFD STMDB 0 1 0 Post Decrement Sto...

Page 105: ...allowed only in privileged modes STMFD R13 R0 R14 Save user mode regs on stack allowed only in privileged modes These instructions may be used to save state on subroutine entry and restore it efficiently on return to the calling routine STMED SP R0 R3 R14 Save R0 to R3 to use as workspace and R14 for returning BL somewhere This nested call will overwrite R14 LDMED SP R0 R3 R15 Restore workspace an...

Page 106: ...determined by the contents of the base register Rn The processor first reads the contents of the swap address Then it writes the contents of the source register Rm to the swap address and stores the old memory contents in the destination register Rd The same register may be specified as both the source and destination The LOCK output goes HIGH for the duration of the read and write operations to s...

Page 107: ... be restarted and the original program continued INSTRUCTION CYCLE TIMES Swap instructions take 1S 2N 1I incremental cycles to execute where S N and I are defined as sequential S cycle non sequential and internal I cycle respectively ASSEMBLER SYNTAX SWP cond B Rd Rm Rn cond Two character condition mnemonic See Table 3 2 B If B is present then byte transfer otherwise word transfer Rd Rm Rn Express...

Page 108: ... fully protected operating system may be constructed RETURN FROM THE SUPERVISOR The PC is saved in R14_svc upon entering the software interrupt trap with the PC adjusted to point to the word after the SWI instruction MOVS PC R14_svc will return to the calling program and restore the CPSR Note that the link mechanism is not re entrant so if the supervisor code wishes to use software interrupts with...

Page 109: ...ce 0x08 B Supervisor SWI entry point EntryTable Addresses of supervisor routines DCD ZeroRtn DCD ReadCRtn DCD WriteIRtn Zero EQU 0 ReadC EQU 256 WriteI EQU 512 Supervisor SWI has routine required in bits 8 23 and data if any in bits 0 7 Assumes R13_svc points to a suitable stack STMFD R13 R0 R2 R14 Save work registers and return address LDR R0 R14 4 Get SWI instruction BIC R0 R0 0xFF000000 Clear t...

Page 110: ...n not be connected to the SC32442B the coprocessor instructions are still described here in full for completeness Remember that any external coprocessor described in this section is a software emulation 31 24 27 19 15 Cond CRm 28 16 11 12 23 20 3 0 Coprocessor operand register 7 5 Coprocessor information 11 8 Coprocessor number 15 12 Coprocessor destination register 19 16 Coprocessor operand regis...

Page 111: ...aracter condition mnemonic See Table 3 2 p The unique number of the required coprocessor expression1 Evaluated to a constant and placed in the CP Opc field cd cn and cm Evaluate to the valid coprocessor register numbers CRd CRn and CRm respectively expression2 Where present is evaluated to a constant and placed in the CP field EXAMPLES CDP p1 10 c1 c2 c3 Request coproc 1 to do operation 10 on CR2 ...

Page 112: ...s or accepts the data and controls the number of words transferred 7 0 Unsigned 8 Bit Immediate Offset 11 8 Coprocessor Number 15 12 Coprocessor Source Destination Register 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Transfer Length 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 2...

Page 113: ...er if W 1 or the old value of the base may be preserved W 0 Note that post indexed addressing modes require explicit setting of the W bit unlike LDR and STR which always write back when post indexed The value of the base register modified by the offset in a pre indexed instruction is used as the address for the transfer of the first word The second word if more than one is transferred will go to o...

Page 114: ...e indexed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn expression offset of expression bytes 3 A post indexed addressing specification Rn expression offset of expression bytes write back the base register set the W bit if is present Rn is an expression evaluating to a valid ARM920T register number NOTES If Rn is R15...

Page 115: ...essor can be moved to the CPSR to control the subsequent flow of execution 31 27 19 15 Cond 28 16 11 12 21 23 20 L CRn Rd 3 0 Coprocessor Operand Register 7 5 Coprocessor Information 11 8 Coprocessor Number 15 12 ARM Source Destination Register 19 16 Coprocessor Source Destination Register 20 Load Store Bit 0 Store to coprocessor 1 Load from coprocessor 21 Coprocessor Operation Mode 31 28 Conditio...

Page 116: ...es spent in the coprocessor busy wait loop ASSEMBLER SYNTAX MCR MRC cond p expression1 Rd cn cm expression2 MRC Move from coprocessor to ARM920T register L 1 MCR Move from ARM920T register to coprocessor L 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor expression1 Evaluated to a constant and placed in the CP Opc field Rd An expression evaluati...

Page 117: ...ken Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present and all coprocessors must refuse to accept it by driving CPA and CPB HIGH INSTRUCTION CYCLE TIMES This instruction takes 2S 1I 1N cycles where S N and I are defined as sequential S cycle non sequential N cycle and internal I cycle ASSEMBLER SYNTAX The assembler has no mnemo...

Page 118: ...ionals for Logical OR CMP Rn p If Rn p OR Rm q THEN GOTO Label BEQ Label CMP Rm q BEQ Label This can be replaced by CMP Rn p CMPNE Rm q If condition not satisfied try other test BEQ Label Absolute Value TEQ Rn 0 Test sign RSBMI Rn Rn 0 and 2 s complement if necessary Multiplication by 4 5 or 6 Run Time MOV Rc Ra LSL 2 Multiply by 4 CMP Rb 5 Test value ADDCS Rc Rc Ra Complete multiply by 5 ADDHI Rc...

Page 119: ...btract if ok ADDCS Rc Rc Rcnt Put relevant bit into result MOVS Rcnt Rcnt LSR 1 Shift control bit MOVNE Rb Rb LSR 1 Halve unless finished BNE Div2 Divide result in Rc remainder in Ra Overflow Detection in the ARM920T 1 Overflow in unsigned multiply with a 32 bit result UMULL Rd Rt Rm Rn 3 to 6 cycles TEQ Rt 0 1 cycle and a register BNE overflow 2 Overflow in signed multiply with a 32 bit result SM...

Page 120: ...xclusive OR feedback rather like a cyclic redundancy check generator Unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length i e 2 32 1 cycles before repetition so this example uses a 33 bit register with taps at bits 33 and 20 The basic algorithm is newbit bit 33 eor bit 20 shift left the 33 bit number and put in newbit at the bottom this operation i...

Page 121: ...odd D 1 MOV Rb Ra LSL n D 1 Rb Ra D MOV Rb Rb LSL n 2 If C MOD 4 1 say C 2 n D 1 D odd n 1 D 1 ADD Rb Ra Ra LSL n D 1 Rb Ra D ADD Rb Ra Rb LSL n 3 If C MOD 4 3 say C 2 n D 1 D odd n 1 D 1 RSB Rb Ra Ra LSL n D 1 Rb Ra D RSB Rb Ra Rb LSL n This is not quite optimal but close An example of its non optimality is multiply by 45 which is done by RSB Rb Ra Ra LSL 2 Multiply by 3 RSB Rb Ra Rb LSL 2 Multip...

Page 122: ... d must be less than c e g 0 1 BIC Rb Ra 3 Get word aligned address LDMIA Rb Rd Rc Get 64 bits containing answer AND Rb Ra 3 Correction factor in bytes MOVS Rb Rb LSL 3 now in bits and test if aligned MOVNE Rd Rd LSR Rb Produce bottom of result word if not aligned RSBNE Rb Rb 32 Get other shift amount ORRNE Rd Rd Rc LSL Rb Combine two halves to get result ...

Page 123: ...ARM INSTRUCTION SET SC32442B RISC MICROPROCESSOR 3 64 NOTES ...

Page 124: ...it versions Thumb instructions at the cost of versatile functions of the ARM instruction sets The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM920T core As the Thumb instructions are compressed ARM instructions the Thumb instructions have the 16 bit format instructions and have some restrictions The restriction by 16 bit format is fully notifi...

Page 125: ...fset5 Rb Rd Rb Rd Offset5 Rd Rd Word8 Word8 SWord7 Rb Cond Rlist Rlist Softset8 Value8 Offset11 Offset Add subtract Move compare add subtract immediate ALU operations Hi register operations branch exchange PC relative load Load store with register offset Load store with immediate offset Load store sign extended byte halfword Load store halfword SP relative load store Load address Add offset to sta...

Page 126: ...nd Condition Codes Set ADC Add with Carry Y Y ADD Add Y Y 1 AND AND Y Y ASR Arithmetic Shift Right Y Y B Unconditional branch Y Bxx Conditional branch Y BIC Bit Clear Y Y BL Branch and Link BX Branch and Exchange Y Y CMN Compare Negative Y Y CMP Compare Y Y Y EOR EOR Y Y LDMIA Load multiple Y LDR Load word Y LDRB Load byte Y LDRH Load halfword Y LSL Logical Shift Left Y Y LDSB Load sign extended b...

Page 127: ...Y Y POP Pop register Y PUSH Push register Y ROR Rotate Right Y Y SBC Subtract with Carry Y Y STMIA Store Multiple Y STR Store word Y STRB Store byte Y STRH Store halfword Y SWI Software Interrupt SUB Subtract Y Y TST Test bits Y Y NOTES 1 The condition codes are unaffected by the format 5 12 and 13 versions of this instruction 2 The condition codes are unaffected by the format 5 version of this in...

Page 128: ...x is shown in Table 4 2 NOTE All instructions in this group set the CPSR condition codes Table 4 2 Summary of Format 1 Instructions OP THUMB Assembler ARM Equipment Action 00 LSL Rd Rs Offset5 MOVS Rd Rs LSL Offset5 Shift Rs left by a 5 bit immediate value and store the result in Rd 01 LSR Rd Rs Offset5 MOVS Rd Rs LSR Offset5 Perform logical shift right on Rs by a 5 bit immediate value and store t...

Page 129: ...s format have an equivalent ARM instruction as shown in Table 4 2 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LSR R2 R5 27 Logical shift right the contents of R5 by 27 and store the result in R2 Set condition codes on the result ...

Page 130: ...tracted from a Lo register The THUMB assembler syntax is shown in Table 4 3 NOTE All instructions in this group set the CPSR condition codes Table 4 3 Summary of Format 2 Instructions OP I THUMB Assembler ARM Equipment Description 0 0 ADD Rd Rs Rn ADDS Rd Rs Rn Add contents of Rn to contents of Rs Place result in Rd 0 1 ADD Rd Rs Offset3 ADDS Rd Rs Offset3 Add 3 bit immediate value to contents of ...

Page 131: ...s in this format have an equivalent ARM instruction as shown in Table 4 3 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD R0 R3 R4 R0 R3 R4 and set condition codes on the result SUB R6 R2 6 R6 R2 6 and set condition codes ...

Page 132: ...HUMB assembler syntax is shown in Table 4 4 NOTE All instructions in this group set the CPSR condition codes Table 4 4 Summary of Format 3 Instructions OP THUMB Assembler ARM Equipment Description 00 MOV Rd Offset8 MOVS Rd Offset8 Move 8 bit immediate value into Rd 01 CMP Rd Offset8 CMP Rd Offset8 Compare contents of Rd with 8 bit immediate value 10 ADD Rd Offset8 ADDS Rd Rd Offset8 Add 8 bit imme...

Page 133: ...nt ARM instruction as shown in Table 4 4 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES MOV R0 128 R0 128 and set condition codes CMP R2 62 Set condition codes on R2 62 ADD R1 255 R1 R1 255 and set condition codes SUB R6 145 R6 R6 145 and set condition codes ...

Page 134: ...d Rd AND Rs 0001 EOR Rd Rs EORS Rd Rd Rs Rd Rd EOR Rs 0010 LSL Rd Rs MOVS Rd Rd LSL Rs Rd Rd Rs 0011 LSR Rd Rs MOVS Rd Rd LSR Rs Rd Rd Rs 0100 ASR Rd Rs MOVS Rd Rd ASR Rs Rd Rd ASR Rs 0101 ADC Rd Rs ADCS Rd Rd Rs Rd Rd Rs C bit 0110 SBC Rd Rs SBCS Rd Rd Rs Rd Rd Rs NOT C bit 0111 ROR Rd Rs MOVS Rd Rd ROR Rs Rd Rd ROR Rs 1000 TST Rd Rs TST Rd Rs Set condition codes on Rd AND Rs 1001 NEG Rd Rs RSBS ...

Page 135: ...nstruction are identical to that of the equivalent ARM instruction EXAMPLES EOR R3 R4 R3 R3 EOR R4 and set condition codes ROR R1 R0 Rotate Right R1 by the value in R0 store the result in R1 and set condition codes NEG R5 R3 Subtract the contents of R3 from zero Store the result in R5 Set condition codes ie R5 R3 CMP R2 R6 Set the condition codes on the result of R2 R6 MUL R0 R7 R0 R7 R0 and set c...

Page 136: ...Table 4 6 NOTES In this group only CMP Op 01 sets the CPSR condition codes The action of H1 0 H2 0 for Op 00 ADD Op 01 CMP and Op 10 MOV is undefined and should not be used Table 4 6 Summary of Format 5 Instructions Op H1 H2 THUMB assembler ARM equivalent Description 00 0 1 ADD Rd Hs ADD Rd Rd Hs Add a register in the range 8 15 to a register in the range 0 7 00 1 0 ADD Hd Rs ADD Hd Hd Rs Add a re...

Page 137: ... Rs Perform branch plus optional state change to address in a register in the range 0 7 11 0 1 BX Hs BX Hs Perform branch plus optional state change to address in a register in the range 8 15 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 6 The instruction cycle times for the THUMB instruction are identical to that of the equivalent A...

Page 138: ...witch from THUMB to ARM state ADR R1 outofTHUMB Load address of outofTHUMB into R1 MOV R11 R1 BX R11 Transfer the contents of R11 into the PC Bit 0 of R11 determines whether ARM or THUMB state is entered ie In this case the state is ARM ALIGN CODE32 outofTHUMB Now processing ARM instructions USING R15 AS AN OPERAND If R15 is used as an operand the value will be the address of the instruction 4 wit...

Page 139: ...7 Summary of PC Relative Load Instruction THUMB assembler ARM equivalent Description LDR Rd PC Imm LDR Rd R15 Imm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the PC Load the word from the resulting address into Rd NOTE The value specified by Imm is a full 10 bit address but must always be word aligned ie with bits 1 0 set to 0 since the assembler places Imm 2 in field W...

Page 140: ...equivalent ARM instruction The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LDR R3 PC 844 Load into R3 the word found at the address formed by adding 844 to PC bit 1 of PC is forced to zero Note that the THUMB opcode will contain 211 as the Word8 value ...

Page 141: ...EGISTER OFFSET 2 0 Source Destination Register 5 3 Base Register 8 6 Offset Register 10 Byte Word Flag 0 Transfer word quantity 1 Transfer byte quantity 11 Load Store Flag 0 Store to memory 1 Load from memory 15 0 0 14 10 6 5 3 2 Rd 1 0 13 12 11 Rb 1 L B 9 8 Ro 0 Figure 4 8 Format 7 ...

Page 142: ...er the value in Rb and the value in Ro Store the byte value in Rd at the resulting address 1 0 LDR Rd Rb Ro LDR Rd Rb Ro Pre indexed word load Calculate the source address by adding together the value in Rb and the value in Ro Load the contents of the address into Rd 1 1 LDRB Rd Rb Ro LDRB Rd Rb Ro Pre indexed byte load Calculate the source address by adding together the value in Rb and the value ...

Page 143: ...of format 8 instructions L B THUMB assembler ARM equivalent Description 0 0 STRH Rd Rb Ro STRH Rd Rb Ro Store halfword Add Ro to base address in Rb Store bits 0 15 of Rd at the resulting address 0 1 LDRH Rd Rb Ro LDRH Rd Rb Ro Load halfword Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to 0 1 0 LDSB Rd Rb Ro LDRSB Rd Rb Ro Load sign extended ...

Page 144: ... cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STRH R4 R3 R0 Store the lower 16 bits of R4 at the address formed by adding R0 to R3 LDSB R2 R7 R1 Load into R2 the sign extended byte found at the address formed by adding R1 to R7 LDSH R3 R4 R2 Load into R3 the sign extended halfword found at the address formed by adding R2 to R4 ...

Page 145: ...MMEDIATE OFFSET 2 0 Source Destination Register 5 3 Base Register 10 6 Offset Register 11 Load Store Flag 0 Store to memory 1 Load from memory 12 Byte Word Flad 0 Transfer word quantity 1 Transfer byte quantity 15 0 0 14 10 6 5 3 2 Rd 1 1 13 12 11 Rb B L Offset5 Figure 4 10 Format 9 ...

Page 146: ...m Store the byte value in Rd at the address 1 1 LDRB Rd Rb Imm LDRB Rd Rb Imm Calculate source address by adding together the value in Rb and Imm Load the byte value at the address into Rd NOTE For word accesses B 0 the value specified by Imm is a full 7 bit address but must be word aligned ie with bits 1 0 set to 0 since the assembler places Imm 2 in the Offset5 field INSTRUCTION CYCLE TIMES All ...

Page 147: ...ses are pre indexed using a 6 bit immediate value The THUMB assembler syntax is shown in Table 4 11 Table 4 11 Halfword Data Transfer Instructions L THUMB assembler ARM equivalent Description 0 STRH Rd Rb Imm STRH Rd Rb Imm Add Imm to base address in Rb and store bits 0 15 of Rd at the resulting address 1 LDRH Rd Rb Imm LDRH Rd Rb Imm Add Imm to base address in Rb Load bits 0 15 from the resulting...

Page 148: ...e times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STRH R6 R1 56 Store the lower 16 bits of R4 at the address formed by adding 56 R1 Note that the THUMB opcode will contain 28 as the Offset5 value LDRH R4 R7 4 Load into R4 the halfword found at the address formed by adding 4 to R7 Note that the THUMB opcode will contain 2 as the Offset5 value ...

Page 149: ...g table Table 4 12 SP Relative Load Store Instructions L THUMB assembler ARM equivalent Description 0 STR Rd SP Imm STR Rd R13 Imm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Store the contents of Rd at the resulting address 1 LDR Rd SP Imm LDR Rd R13 Imm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Load the word from the r...

Page 150: ...an equivalent ARM instruction as shown in Table 4 12 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STR R4 SP 492 Store the contents of R4 at the address formed by adding 492 to SP R13 Note that the THUMB opcode will contain 123 as the Word8 value ...

Page 151: ...ler ARM equivalent Description 0 ADD Rd PC Imm ADD Rd R15 Imm Add Imm to the current value of the program counter PC and load the result into Rd 1 ADD Rd SP Imm ADD Rd R13 Imm Add Imm to the current value of the stack pointer SP and load the result into Rd NOTE The value specified by Imm is a full 10 bit value but this must be word aligned ie with bits 1 0 set to 0 since the assembler places Imm 2...

Page 152: ...ction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD R2 PC 572 R2 PC 572 but don t set thecondition codes bit 1 of PC is forced to zero Note that the THUMB opcode willcontain 143 as the Word8 value ADD R6 SP 212 R6 SP R13 212 but don tset the condition codes Note that the THUMB opcode will contain 53 as the Word 8 value ...

Page 153: ...e stack pointer SP NOTE The offset specified by Imm can be up to 508 but must be word aligned ie with bits 1 0 set to 0 since the assembler converts Imm to an 8 bit sign magnitude number before placing it in field SWord7 The condition codes are not set by this instruction INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 14 The instructi...

Page 154: ...hown in Table 4 15 NOTE The stack is always assumed to be Full Descending Table 4 15 PUSH and POP Instructions L B THUMB assembler ARM equivalent Description 0 0 PUSH Rlist STMDB R13 Rlist Push the registers specified by Rlist onto the stack Update the stack pointer 0 1 PUSH Rlist LR STMDB R13 Rlist R14 Push the Link Register and the registers specified by Rlist if any onto the stack Update the st...

Page 155: ... for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES PUSH R0 R4 LR Store R0 R1 R2 R3 R4 and R14 LR at the stack pointed to by R13 SP and update R13 Useful at start of a sub routine to save workspace and return address POP R2 R6 PC Load R2 R6 and R15 PC from the stack pointed to by R13 SP and update R13 Useful to restore workspace and return from sub routine ...

Page 156: ...0 STMIA Rb Rlist STMIA Rb Rlist Store the registers specified by Rlist starting at the base address in Rb Write back the new base address 1 LDMIA Rb Rlist LDMIA Rb Rlist Load the registers specified by Rlist starting at the base address in Rb Write back the new base address INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 16 The instruc...

Page 157: ...he THUMB assembler syntax is shown in the following table Table 4 17 The Conditional Branch Instructions L THUMB assembler ARM equivalent Description 0000 BEQ label BEQ label Branch if Z set equal 0001 BNE label BNE label Branch if Z clear not equal 0010 BCS label BCS label Branch if C set unsigned higher or same 0011 BCC label BCC label Branch if C clear unsigned lower 0100 BMI label BMI label Br...

Page 158: ...el Branch if Z set or N set and V clear or N clear and V set less than or equal NOTES 1 While label specifies a full 9 bit two s complement address this must always be halfword aligned ie with bit 0 set to 0 since the assembler actually places label 1 in field SOffset8 2 Cond 1110 is undefined and should not be used Cond 1111 creates the SWI instruction see INSTRUCTION CYCLE TIMES All instructions...

Page 159: ... equivalent Description SWI Value 8 SWI Value 8 Perform Software Interrupt Move the address of the next instruction into LR move CPSR to SPSR load the SWI vector address 0x8 into the PC Switch to ARM state and enter SVC mode NOTE Value8 is used solely by the SWI handler it is ignored by the processor INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as show...

Page 160: ... instruction Table 4 19 Summary of Branch Instruction THUMB assembler ARM equivalent Description B label BAL label halfword offset Branch PC relative Offset11 1 where label is PC 2048 bytes NOTE The address specified by label is a full 12 bit two s complement address but must always be halfword aligned ie bit 0 set to 0 since the assembler places label 1 in the Offset11 field EXAMPLES here B here ...

Page 161: ... Instruction 1 H 0 In the first instruction the Offset field contains the upper 11 bits of the target address This is shifted left by 12 bits and added to the current PC address The resulting address is placed in LR Instruction 2 H 1 In the second instruction the Offset field contains an 11 bit representation lower half of the target address This is shifted left by 1 bit and added to LR LR which n...

Page 162: ...bler ARM equivalent Description 0 BL label none LR PC OffsetHigh 12 1 temp next instruction address PC LR OffsetLow 1 LR temp 1 EXAMPLES BL faraway Unconditionally Branch to faraway next and place following instruction address ie next in R14 the Link register and set bit 0 of LR high Note that the THUMB opcodes will contain the number of halfwords to offset faraway Must be Half word aligned ...

Page 163: ...ion rather than using a sequence of 4 or more instructions Thumb ARM 1 Multiplication by 2 n 1 2 4 8 LSL Ra Rb LSL n MOV Ra Rb LSL n 2 Multiplication by 2 n 1 3 5 9 17 LSL Rt Rb n ADD Ra Rb Rb LSL n ADD Ra Rt Rb 3 Multiplication by 2 n 1 3 7 15 LSL Rt Rb n RSB Ra Rb Rb LSL n SUB Ra Rt Rb 4 Multiplication by 2 n 2 4 8 LSL Ra Rb n MOV Ra Rb LSL n MVN Ra Ra RSB Ra Ra 0 5 Multiplication by 2 n 1 3 7 1...

Page 164: ...1 if negative ASR R0 R1 31 Get 0 or 1 in R3 depending on sign of R1 EOR R1 R0 EOR with 1 0 FFFFFFFF if negative SUB R1 R0 and ADD 1 SUB 1 to get abs value Save signs 0 or 1 in R0 R2 for later use in determining sign of quotient remainder PUSH R0 R2 Justification shift 1 bit at a time until divisor R0 value is just than dividend R1 value To do this shift dividend right by 1 and stop as soon as shif...

Page 165: ...hifted out later ANDS a4 a1 80000000 RSBMI a1 a1 0 EORS ip a4 a2 ASR 32 ip bit 31 sign of result ip bit 30 sign of a2 RSBCS a2 a2 0 Central part is identical code to udiv without MOV a4 0 which comes for free as part of signed entry sequence MOVS a3 a1 BEQ divide_by_zero just_l Justification stage shifts 1 bit at a time CMP a3 a2 LSR 1 MOVLS a3 a3 LSL 1 NB LSL 1 is always OK if LS succeeds BLO s_l...

Page 166: ...Take argument in a1 returns quotient in a1 remainder in a2 MOV a2 a1 LSR a3 a1 2 SUB a1 a3 LSR a3 a1 4 ADD a1 a3 LSR a3 a1 8 ADD a1 a3 LSR a3 a1 16 ADD a1 a3 LSR a1 3 ASL a3 a1 2 ADD a3 a1 ASL a3 1 SUB a2 a3 CMP a2 10 BLT FT0 ADD a1 1 SUB a2 10 0 MOV pc lr ARM Code udiv10 Take argument in a1 returns quotient in a1 remainder in a2 SUB a2 a1 10 SUB a1 a1 a1 lsr 2 ADD a1 a1 a1 lsr 4 ADD a1 a1 a1 lsr ...

Page 167: ...THUMB INSTRUCTION SET SC32442B RISC MICROPROCESSOR 4 44 NOTES ...

Page 168: ...Address space 128Mbytes per bank total 1GB 8 banks Programmable access size 8 16 32 bit for all banks except bank0 16 32 bit Total 8 memory banks Six memory banks for ROM SRAM etc Remaining two memory banks for ROM SRAM SDRAM etc Seven fixed memory bank start address One flexible memory bank start address and programmable bank size Programmable access cycles for all memory banks External wait to e...

Page 169: ...M nGCS1 SROM nGCS0 OM 1 0 01 10 OM 1 0 00 Not using NAND flash for boot ROM Using NAND flash for boot ROM Figure 5 1 SC32442B Memory Map after Reset Table 5 1 Bank 6 7 Addresses Address 2MB 4MB 8MB 16MB 32MB 64MB 128MB Bank 6 Start address 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 End address 0x301F_FFFF 0X303F_FFFF 0X307F_FFFF 0X30FF_FFFF 0X31FF_FFFF 0X33...

Page 170: ...nk map to 0x0000_0000 the bus width of BANK0 should be determined before the first ROM access which will depend on the logic level of OM 1 0 at Reset OM1 Operating Mode 1 OM0 Operating Mode 0 Booting ROM Data width 0 0 Nand Flash Mode 0 1 16 bit 1 0 32 bit 1 1 Test Mode MEMORY SROM SDRAM ADDRESS PIN CONNECTIONS MEMORY ADDR PIN SC32442B ADDR 8 bit DATA BUS SC32442B ADDR 16 bit DATA BUS SC32442B ADD...

Page 171: ... 512K x 32 x 4B x 1 16MB x32 16Mb 2M x 4 x 2B x 8 A23 x8 64Mb 8M x 4 x 2B x 2 x8 4M x 4 x 4B x 2 A 23 22 x16 4M x 8 x 2B x 2 A23 x16 2M x 8 x 4B x 2 A 23 22 x32 2M x 16 x 2B x 2 A23 x32 1M x 16 x 4B x 2 A 23 22 x8 128Mb 4M x 8 x 4B x 1 x16 2M x 16 x 4B x 1 32MB x16 64Mb 8M x 4 x 2B x 4 A24 x16 4M x 4 x 4B x 4 A 24 23 x32 4M x 8 x 2B x 4 A24 x32 2M x 8 x 4B x 4 A 24 23 x16 128Mb 4M x 8 x 4B x 2 x32...

Page 172: ... nOE duration should be prolonged by the external nWAIT pin while the memory bank is active nWAIT is checked from tacc 1 nOE will be de asserted at the next clock after sampling nWAIT is high The nWE signal have the same relation with nOE Tacs Tcos Tacc 4 HCLK ADDR nGCS nOE nWAIT DATA R Delayed Sampling nWAIT Figure 5 2 SC32442B External nWAIT Timing Diagram Tacc 4 ...

Page 173: ...2B will respond by lowering nXBACK If nXBACK L the address data bus and memory control signals are in Hi Z state as shown in Table 1 1 After nXBREQ is de asserted the nXBACK will also be de asserted HCLK SCKE A 24 0 D 31 0 nGCS nOE nWE nWBE nXBREQ nXBACK SCLK 1clk Figure 5 3 SC32442B nXBREQ nXBACK Timing Diagram ...

Page 174: ...E Figure 5 4 Memory Interface with 8 bit ROM A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 nWBE0 nOE nGCSn A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D8 D9 D10 D11 D12 D13 D14 D15 nWBE1 nOE nGCSn A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1...

Page 175: ...A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D16 D17 D18 D19 D20 D21 D22 D23 nWBE2 nOE nGCSn A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE D24 D25 D26 D27 D28 D29 D30 D31 nWBE3 nOE nGCSn Figure 5 6 Memory Interface with 8 bit ROM x 4 A1 A2 A3 A4 A5...

Page 176: ...M A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nWE nOE nCS nWE nOE nGCSn nUB nLB nBE1 nBE0 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 D16 D17 D18 D19 D20 D21 D22 D13 D24 D25 D26 D27 D28 D29 D30 D31 ...

Page 177: ...4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 BA0 BA1 LDQM UDQM A24 A25 DQM0 DQM1 SCKE SCLK SCKE SCLK nSCS0 nSRAS nSCAS nWE nSCS nSRAS nSCAS nWE A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ...

Page 178: ...ER DEC 13 2002 5 11 PROGRAMMABLE ACCESS CYCLE Tcoh Tcos Tacs HCLK A 24 0 nGCS nOE nWE nWBE D 31 0 R D 31 0 W Tacc Tacp Tcah Tacs 1 cycle Tcos 1 cycle Tacc 3 cycles Tacp 2 cycles Tcoh 1 cycle Tcah 2 cycles Figure 5 12 SC32442B nGCS Timing Diagram ...

Page 179: ...S ADDR A10 AP RA nSRAS BA DATA CL2 DATA CL3 nWE DQM Trp Trcd RA Ca Da Da BA BA Cb Cc Cd Ce Db Dc Dd De Db Dc Dd De BA BA BA BA BA Bank Precharge Row Active Write Read CL 2 CL 3 BL 1 Trp 2 cycle Tcas 2 cycle Trcd 2 cycle Tcp 2 cycle Figure 5 13 SC32442B SDRAM Timing Diagram ...

Page 180: ... ST5 23 Determines SRAM for using UB LB for bank 5 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 0 WS5 22 Determines WAIT status for bank 5 0 WAIT disable 1 WAIT enable 0 DW5 21 20 Determines data bus width for bank 5 00 8 bit 01 16 bit 10 32 bit 11 reserved 0 ST4 19 Determines SRAM for using UB LB for bank 4 0 Not using UB LB The pins are dedicated...

Page 181: ... 0 0 WS1 6 Determines WAIT status for bank 1 0 WAIT disable 1 WAIT enable 0 DW1 5 4 Determines data bus width for bank 1 00 8 bit 01 16 bit 10 32 bit 11 reserved 0 DW0 2 1 Indicate data bus width for bank 0 read only 01 16 bit 10 32 bit The states are selected by OM 1 0 pins Reserved 0 Reserve to 0 0 Note 1 All types of master clock in this memory controller correspond to the bus clock For example...

Page 182: ...acs 14 13 Address set up time before nGCSn 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks 00 Tcos 12 11 Chip selection set up time before nOE 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks 00 Tacc 10 8 Access cycle 000 1 clock 001 2 clocks 010 3 clocks 011 4 clocks 100 6 clocks 101 8 clocks 110 10 clocks 111 14 clocks Note When nWAIT signal is used Tacc 4 clocks 111 Tcoh 7 6 Chip selection hold time...

Page 183: ...lection set up time before nOE 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks 00 Tacc 10 8 Access cycle 000 1 clock 001 2 clocks 010 3 clocks 011 4 clocks 100 6 clocks 101 8 clocks 110 10 clocks 111 14 clocks 111 Tcoh 7 6 Chip selection hold time after nOE 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks 00 Tcah 5 4 Address hold time after nGCSn 00 0 clock 01 1clock 10 2 clocks 11 4 clocks 00 Tacp 3 2...

Page 184: ... are driven to the appropriate level 0 Trp 21 20 SDRAM RAS pre charge Time 00 2 clocks 01 3 clocks 10 4 clocks 11 Not support 10 Tsrc 19 18 SDRAM Semi Row cycle time 00 4 clocks 01 5 clocks 10 6 clocks 11 7 clocks SDRAM Row cycle time Trc Tsrc Trp If Trp 3clocks Tsrc 7clocks Trc 3 7 10clocks 11 Reserved 17 16 Not used 00 Reserved 15 11 Not used 0000 Refresh Counter 10 0 SDRAM refresh count value R...

Page 185: ...ion 0 Reserved 6 Not used 0 SCKE_EN 5 SDRAM power down mode enable control by SCKE 0 SDRAM power down mode disable 1 SDRAM power down mode enable 0 SCLK_EN 4 SCLK is enabled only during SDRAM access cycle for reducing power consumption When SDRAM is not accessed SCLK becomes L level 0 SCLK is always active 1 SCLK is active only during the access recommended 0 Reserved 3 Not used 0 BK76MAP 2 0 BANK...

Page 186: ... Initial State Reserved 11 10 Not used WBL 9 Write burst length 0 Burst Fixed 1 Reserved x TM 8 7 Test mode 00 Mode register set Fixed 01 10 and 11 Reserved xx CL 6 4 CAS latency 000 1 clock 010 2 clocks 011 3 clocks Others reserved xxx BT 3 Burst type 0 Sequential Fixed 1 Reserved x BL 2 0 Burst length 000 1 Fixed Others Reserved xxx Note MRSR register must not be reconfigured while the code is r...

Page 187: ...MEMORY CONTROLLER SC32442B RISC MICROPROCESSOR 5 20 NOTES ...

Page 188: ... the NAND flash data validity will be checked Upon the completion of the copy the main program will be executed on the SDRAM FEATURES 1 Auto boot The boot code is transferred into 4 kbytes Steppingstone during reset After the transfer the boot code will be executed on the Steppingstone 2 NAND Flash memory I F Support 256Words 512Bytes 1KWords and 2KBytes Page 3 Software mode User can directly acce...

Page 189: ...UTO BOOT CORE ACCESS Boot Code USER ACCESS Figure 6 2 NAND Flash Controller Boot Loader Block Diagram During reset Nand flash controller will get information about the connected NAND flash through Pin status NCON Adv flash GPG13 Page size GPG14 Address cycle GPG15 Bus width refer to PIN CONFIGURATION After power on or system reset is occurred the NAND Flash controller load automatically the 4 KByt...

Page 190: ...ycle NCON 1 GPG15 NAND flash memory bus width selection 0 8 bit bus width 1 16 bit bus width NOTE The configuration pin NCON GPG 15 13 will be fetched during reset In normal status these pins must be set as input so that the pin status is not to be changed when enters Sleep mode by software or unexpected cause NAND FLASH MEMORY CONFIGURATION TABLE NCON0 GPG13 GPG14 GPG15 0 256Words 0 3 Addr 0 Norm...

Page 191: ...C MICROPROCESSOR 6 4 NAND FLASH MEMORY TIMING HCLK CLE ALE nWE TACLS TWRPH0 TWRPH1 DATA COMMAND ADDRESS Figure 6 3 CLE ALE Timing TACLS 1 TWRPH0 0 TWRPH1 0 HCLK nWE nRE DATA DATA TWRPH0 TWRPH1 Figure 6 4 nWE nRE Timing TWRPH0 0 TWRPH1 0 ...

Page 192: ... the command register the NAND Flash Memory command cycle 2 Writing to the address register the NAND Flash Memory address cycle 3 Writing to the data register write data to the NAND Flash Memory write cycle 4 Reading from the data register read data from the NAND Flash Memory read cycle 5 Reading main ECC registers and Spare ECC registers read data from the NAND Flash Memory NOTE In the software m...

Page 193: ...nterface A Word Access Register Endian Bit 31 24 Bit 23 16 Bit 15 8 Bit 7 0 NFDATA Little 4th I O 7 0 3rd I O 7 0 2nd I O 7 0 1st I O 7 0 NFDATA Big 1st I O 7 0 2nd I O 7 0 3rd I O 7 0 4th I O 7 0 B Half word Access Register Endian Bit 31 24 Bit 23 16 Bit 15 8 Bit 7 0 NFDATA Little Invalid value Invalid value 2nd I O 7 0 1st I O 7 0 NFDATA Big Invalid value Invalid value 1st I O 7 0 2nd I O 7 0 C ...

Page 194: ... to 16 bytes ECC Parity code generation 28bit ECC Parity Code 22bit Line parity 6bit Column Parity 14bit ECC Parity Code 8bit Line parity 6bit Column Parity 2048 BYTE ECC PARITY CODE ASSIGNMENT TABLE DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 MECCn_0 P64 P64 P32 P32 P16 P16 P8 P8 MECCn_1 P1024 P1024 P512 P512 P256 P256 P128 P128 MECCn_2 P4 P4 P2 P2 P1 P1 P2048 P2048 MECCn_3 P8192 P8192 P4096 ...

Page 195: ...erates ECC parity code for all read write data So you have to reset ECC value by writing the InitECC NFCONT 4 bit as 1 and have to clear theMainECCLock NFCONT 5 bit to 0 Unlock before read or write data MainECCLock NFCONT 5 and SpareECCLock NFCONT 6 control whether ECC Parity code is generated or not 2 Whenever data is read or written the ECC module generates ECC parity code on register NFMECC0 1 ...

Page 196: ... Used SDRAM BANK7 nGCS7 0x3800_0000 SDRAM BANK7 nGCS7 SDRAM BANK6 nGCS6 0x3000_0000 SDRAM BANK6 nGCS6 SROM BANK5 nGCS5 SROM BANK5 nGCS5 0x2000_0000 0x2800_0000 SROM BANK4 nGCS4 SROM BANK3 nGCS3 SROM BANK2 nGCS2 0x1000_0000 0x1800_0000 0x0800_0000 SROM BANK1 nGCS1 SROM BANK4 nGCS4 SROM BANK3 nGCS3 SROM BANK2 nGCS2 SROM BANK1 nGCS1 SROM BANK0 nGCS0 BootSRAM 4KB 0x0000_0000 OM 1 0 01 10 OM 1 0 00 0x4...

Page 197: ... B WE ALE CLE CE RE Rn B nFWE ALE CLE nFCE nFRE DATA 7 DATA 6 DATA 5 DATA 4 DATA 3 DATA 2 DATA 1 DATA 0 I O7 I O6 I O5 I O4 I O3 I O2 I O1 I O0 R B WE ALE CLE CE RE Rn B nFWE ALE CLE nFCE nFRE DATA 15 DATA 14 DATA 13 DATA 12 DATA 11 DATA 10 DATA 9 DATA 8 Figure 6 2 Two 8 bit NAND Flash Memory Interface I O15 I O14 I O13 I O12 I O11 I O10 I O9 I O8 R B WE ALE CLE CE RE I O7 I O6 I O5 I O4 I O3 I O2...

Page 198: ...lash Configuration register 0x0000100X NFCONF Bit Description Initial State Reserved 15 14 Reserved TACLS 13 12 CLE ALE duration setting value 0 3 Duration HCLK x TACLS 01 Reserved 11 Reserved 0 TWRPH0 10 8 TWRPH0 duration setting value 0 7 Duration HCLK x TWRPH0 1 000 Reserved 7 Reserved 0 TWRPH1 6 4 TWRPH1 duration setting value 0 7 Duration HCLK x TWRPH1 1 000 ...

Page 199: ...p mode After reset the GPG13 can be used as general I O port or External interrupt H W Set GPG13 AddrCycle Read only 1 NAND flash memory Address cycle for auto booting AdvFlash AddrCycle When AdvFlash is 0 0 3 address cycle 1 4 address cycle When AdvFlash is 1 0 4 address cycle 1 5 address cycle This bit is determined by GPG14pin status during reset and wake up from sleep mode After reset the GPG1...

Page 200: ...ock 12 Soft Lock configuration 0 Disable lock 1 Enable lock Soft lock area can be modified at any time by software When it is set to 1 the area setting in NFSBLK 0x4E000038 to NFEBLK 0x4E00003C 1 is unlocked and except this area write or erase command will be invalid and only read command is valid When you try to write or erase locked area the illegal access will be occur NFSTAT 3 bit will be set ...

Page 201: ...ister is NFMECC0 1 0x4E00002C 30 1 InitECC 4 Initialize ECC decoder encoder Write only 1 Initialize ECC decoder encoder 0 Reserved 2 3 Reserved 00 Reg_nCE 1 NAND Flash Memory nFCE signal control 0 Force nFCE to low Enable chip select 1 Force nFCE to High Disable chip select Note During boot time it is controlled automatically This value is only valid while MODE bit is 1 1 MODE 0 NAND Flash control...

Page 202: ...S REGISTER Register Address R W Description Reset Value NFADDR 0x4E00000C R W NAND Flash address set register 0x0000XX00 REG_ADDR Bit Description Initial State Reserved 15 8 Reserved 0x00 NFADDR 7 0 NAND Flash memory address value 0x00 DATA REGISTER Register Address R W Description Reset Value NFDATA 0x4E000010 R W NAND Flash data register 0xXXXX NFDATA Bit Description Initial State NFDATA 31 0 NA...

Page 203: ...ECC value from NAND flash memory 0x00 ECCData0_1 15 8 1st ECC for I O 15 8 0x00 ECCData0_0 7 0 1st ECC for I O 7 0 Note In Software mode Read this register when you need to read 1st ECC value from NAND flash memory This register has same read function of NFDATA 0x00 Note Only word access is valid NFMECCD1 Bit Description Initial State ECCData3_1 31 24 4th ECC for I O 15 8 0x00 ECCData3_0 23 16 4th...

Page 204: ...nitial State ECCData1_1 31 24 2nd ECC for I O 15 8 0x00 ECCData1_0 23 16 2nd ECC for I O 7 0 Note In Software mode Read this register when you need to read 2nd ECC value from NAND flash memory 0x00 ECCData0_1 15 8 1st ECC for I O 15 8 0x00 ECCData0_0 7 0 1st ECC for I O 7 0 Note In Software mode Read this register when you need to read 1st ECC value from NAND flash memory This register has same re...

Page 205: ...legal access program erase to the memory makes this bit set 0 illegal access is not detected 1 illegal access is detected 0 RnB_TransDetect 2 When RnB low to high transition is occurred this value set and issue interrupt if enabled To clear this value write 1 0 RnB transition is not detected 1 RnB transition is detected Transition configuration is set in RnB_TransMode NFCONT 8 0 nCE Read only 1 Th...

Page 206: ...r 1 0 Indicates whether main data area bit fail error occurred 00 No Error 01 1 bit error correctable 10 Multiple error 11 ECC area error 00 Note The above values are only valid when both ECC register and ECC status register have valid value NFESTAT1 Bit Description Initial State SErrorDataNo 24 21 In spare area Indicates which number data is error 00 SErrorBitNo 20 18 In spare area Indicates whic...

Page 207: ...6 ECC2 data 15 8 0xXX MECC1_1 15 8 ECC1 data 15 8 0xXX MECC1_0 7 0 ECC0 data 15 8 0xXX Note The NAND flash controller generate NFMECC0 1 when read or write main area data while the MainECCLock NFCONT 5 bit is 0 Unlock SPARE AREA ECC STATUS REGISTER Register Address R W Description Reset Value NFSECC 0x4E000034 R NAND Flash ECC register for I O 15 0 0xXXXXXX NFSECC Bit Description Initial State SEC...

Page 208: ...16 The 3rd block address of the block erase operation 0x00 SBLK_ADDR1 15 8 The 2nd block address of the block erase operation 0x00 SBLK_ADDR0 7 0 The 1st block address of the block erase operation Only bit 7 5 are valid 0x00 Note Advance Flash s block Address start from 3 address cycle So block address register only needs 3 bytes NFEBLK Bit Description Initial State EBLK_ADDR2 23 16 The 3rd block ...

Page 209: ... lock bit NFCONT 12 is enabled But cannot be changed when Lock tight bit NFCONT 13 is set when Lock tight 1 or SoftLock 1 NAND flash memory Locked area Read only Prorammable Readable Area Locked area Read only NFSBLK Address High Low NFEBLK NFEBLK 1 NFSBLK NFEBLK Locked Area Read only When NFSBLK NFEBLK ...

Page 210: ...CLK directly as FCLK in the SC32442B without PLL In this mode the power consumption depends on the frequency of the external clock only The power consumption due to PLL is excluded IDLE mode The block disconnects clocks FCLK only to the CPU core while it supplies clocks to all other peripherals The IDLE mode results in reduced power consumption due to CPU core Any interrupt request to CPU can be w...

Page 211: ... the SC32442B The OM 3 2 status is latched internally by referring the OM3 and OM2 pins at the rising edge of nRESET Table 7 1 Clock Source Selection at Boot Up Mode OM 3 2 MPLL State UPLL State Main Clock source USB Clock Source 00 On On Crystal Crystal 01 On On Crystal EXTCLK 10 On On EXTCLK Crystal 11 On On EXTCLK EXTCLK NOTE 1 Although the MPLL starts just after a reset the MPLL output Mpll is...

Page 212: ... ADC UART 0 1 2 PWM I2C GPIO RTC SPI 0 1 USB Device ARM920T Interrupt Controller LCD Controller H_LCD P_SDI P_GPIO P_ADC P_RTC P_UART P_SPI P_I2S P_I2C P_PWM P_USB H_Nand FCLK PCLK HCLK UCLK Power Management Block MPLLin CLK UPLL CLK HCLK PCLK RTC XTAL CLK CLKOUT XTIpll XTOpll EXTCLK P 5 0 M 7 0 S 1 0 OM 3 2 P 5 0 M 7 0 S 1 0 USB Host I F H_USB TIC H_CAM CAM ExtMater DIVN_UPLL 1 1 or 1 2 CAMDIVN M...

Page 213: ...acking signal when the difference is detected The Fref means the reference frequency as shown in the Figure 7 2 Charge Pump PUMP The charge pump converts PFD control signals into a proportional change in voltage across the external filter that drives the VCO Loop Filter The control signal which the PFD generates for the charge pump may generate large excursions ripples each time the Fvco is compar...

Page 214: ...5 0 Fvco PUMP VCO Divider S Fref MPLL UPLL R C Internal CLF External MPLLCAP UPLLCAP Figure 7 2 PLL Phase Locked Loop Block Diagram EXTCLK XTIpll XTOpll EXTCLK XTIpll XTOpll External OSC a X TAL Oscillation OM 3 2 00 b External Clock Source OM 3 2 11 VDD VDD CEXT CEXT Figure 7 3 Main Oscillator Circuit Examples ...

Page 215: ... operate according to the default PLL configuration However PLL is commonly known to be unstable after power on reset so Fin is fed directly to FCLK instead of the Mpll PLL output before the software newly configures the PLLCON Even if the user does not want to change the default value of PLLCON register after reset the user should write the same value into PLLCON register by software The PLL rest...

Page 216: ... Mpll PMS setting PLL Lock time FCLK It changes to new PLL clock after automatic lock time Figure 7 5 Changing Slow Clock by Setting PMS Value USB Clock Control USB host interface and USB device interface needs 48Mhz clock In the SC32442B the USB dedicated PLL UPLL generates 48Mhz for USB UCLK does not fed until the PLL UPLL is configured Condition UCLK State UPLL State After reset XTlpll or EXTCL...

Page 217: ...1 0 FCLK FCLK 2 FCLK 2 1 2 2 1 1 FCLK FCLK 2 FCLK 4 1 2 4 3 0 0 0 FCLK FCLK 3 FCLK 3 1 3 3 3 1 0 0 FCLK FCLK 3 FCLK 6 1 3 6 3 0 1 0 FCLK FCLK 6 FCLK 6 1 6 6 3 1 1 0 FCLK FCLK 6 FCLK 12 1 6 12 2 0 0 0 FCLK FCLK 4 FCLK 4 1 4 4 2 1 0 0 FCLK FCLK 4 FCLK 8 1 4 8 2 0 0 1 FCLK FCLK 8 FCLK 8 1 8 8 2 1 0 1 FCLK FCLK 8 FCLK 16 1 8 16 After setting PMS value it is required to set CLKDIVN register The value s...

Page 218: ...ast bus mode to the asynchronous bus mode using following instructions SC32442 does not support synchronous bus mode MMU_SetAsyncBusMode mrc p15 0 r0 c1 c0 0 orr r0 r0 R1_nF OR R1_iA mcr p15 0 r0 c1 c0 0 If HDIVN is not 0 and the CPU bus mode is the fast bus mode the CPU will operate by the HCLK This feature can be used to change the CPU frequency as a half or more without affecting the HCLK and P...

Page 219: ...wing section describes each power management mode The transition between the modes is not allowed freely Please see Figure 7 8 for available transitions among the modes INTCNTL Power Management FCLK Input Clock FCLK defination If SLOW mode FCLK input clock divider ratio If Normal mode P M S value FCLK MPLL clock Mpll ARM920T HCLK PCLK UPLL 96 48 MHz BUSCNTL MEMCNTL ARB DMA ExtMaster LCDCNTL Nand F...

Page 220: ... Each Power Mode Mode ARM920T AHB Modules 1 WDT Power Management GPIO 32 768kHz RTC clock APB Modules 2 USBH LCD NAND NORMAL O O O SEL O SEL IDLE X O O SEL O SEL SLOW O O O SEL O SEL STOP X X Wait for wake up event Previous state O X Deep STOP OFF X Wait for wake up event Previous state O X SLEEP OFF OFF Wait for wake up event Previous state O OFF NOTES 1 USB host LCD and NAND are excluded 2 WDT i...

Page 221: ...OW and CLKDIVN Register Settings for SLOW Clock example SLOW_VAL FCLK HCLK PCLK UCLK 1 1 Option HDIVN 0 1 2 Option HDIVN 1 1 1 Option PDIVN 0 1 2 Option PDIVN 1 0 0 0 EXTCLK or XTIpll 1 EXTCLK or XTIpll 1 EXTCLK or XTIpll 2 HCLK HCLK 2 48 MHz 0 0 1 EXTCLK or XTIpll 2 EXTCLK or XTIpll 2 EXTCLK or XTIpll 4 HCLK HCLK 2 48 MHz 0 1 0 EXTCLK or XTIpll 4 EXTCLK or XTIpll 4 EXTCLK or XTIpll 8 HCLK HCLK 2 ...

Page 222: ...L clock after slow mode off Figure 7 9 Issuing Exit_from_Slow_mode Command in PLL on State If the user switches from SLOW mode to Normal mode by disabling the SLOW_BIT in the CLKSLOW register after PLL lock time the frequency is changed just after SLOW mode is disabled Figure 7 12 Please check for the figure number correctly shows the timing diagram Mpll FCLK SLOW_BIT Divided OSC clock MPLL_OFF So...

Page 223: ...requency is changed just after the PLL lock time Figure 7 13 Please check for the figure number correctly shows the timing diagram Mpll FCLK SLOW_BIT Divided OSC clock MPLL_OFF Hardware lock time PLL off PLL on Slow mode enable It changes to PLL clock after lock time automatically Slow mode disable Figure 7 11 Issuing Exit_from_Slow_mode Command and the Instant PLL_on Command Simultaneously ...

Page 224: ...ll interrupts are masked EINT can wake up SC32442B with the setting of EXINT register The SC32442B can exit from STOP mode by EINT external interrupts TICK or RTC alarm During the wake up sequences the crystal oscillator and PLL may begin to operate The lock time is also needed to stabilize FCLK The lock time is inserted automatically and guaranteed by power management logic During this lock time ...

Page 225: ...n self refresh mode All interrupts should be masked because DRAM can t be accessed when it s in self refresh mode Even though all interrupts are masked EINT can wake up SC32442B with the setting of EXINT register When wakeup the Deep STOP Arm jumped to reset handler therefore arm changed Fast mode User must be set to Async mode of ARM920T The SC32442B can exit from Deep STOP mode by EINT external ...

Page 226: ...D or EINTPEND set Although a wake up source is issued and the corresponding bit of EINTMASK is masked the wake up will occur and the corresponding bit of SRCPND or EINTPEND will not be set 4 Set USB pads as suspend mode MISCCR 13 12 11b 5 Save some meaning values into GSTATUS 4 3 register These register are preserved during SLEEP mode 6 Configure MISCCR 1 0 for the pull up resisters on the data bu...

Page 227: ...EP mode 7 For EINT 3 0 check the SRCPND register For EINT 15 4 check the EINTPEND instead of SRCPND SRCPND will not be set although some bits of EINTPEND are set Table 7 4 Pin configuration table in Sleep mode Pin Condition Guid of Pin Configuration which are configured as Input Pull down Enable GPIO Pin which are configured as Ouput Pull down Disable and Output Low Input Pin which doesn t have in...

Page 228: ...VDDiarm VDDMPLL and VDDUPLL may be turned off the other power pins have to be supplied SC32442A Power CTRL Alive Block RTC Alarm EINT External Interrupt 3 3V 2 5V Power PWREN VDDi VDDiarm VDDMPLL VDDUPLL Core Peripherals RTC I O Regulator 1 35V 1 5V EN 1 35V Power VDDalive ADC 1 8V 3 6V Memory Interface 1 8V 3 3V Figure 7 13 SLEEP Mode NOTE During sleep mode if you don t use Touch Screen panel Tou...

Page 229: ...ntrol logic receives ACK signal from the CPU wrapper PLL On Off The PLL can only be turned off for low power consumption in slow mode If the PLL is turned off in any other mode MCU operation is not guaranteed When the processor is in SLOW mode and tries to change its state into other state with the PLL turned on then SLOW_BIT should be clear to move to another state after PLL stabilization Pull up...

Page 230: ... current consumption in SLEEP mode Battery Fault Signal nBATT_FLT There are two functions in nBATT_FLT pin they are as follows When CPU is not in SLEEP mode nBATT_FLT pin will cause the interrupt request by setting BATT_FUNC MISCCR 22 20 as 10x b The interrupt attribute of the nBATT_FLT is L level triggered While CPU is in SLEEP mode assertion of the nBATT_FLT will prohibit the wake up from the sl...

Page 231: ...K 300uS M_LTIME 1000uS 0xFFFF MPLL Control Register Mpll 2 m Fin p 2s m MDIV 8 p PDIV 2 s SDIV UPLL Control Register Upll m Fin p 2s m MDIV 8 p PDIV 2 s SDIV PLL Value Selection Guide MPLLCON 1 Fout 2 m Fin p 2s Fvco 2 m Fin p where m MDIV 8 p PDIV 2 s SDIV 2 300MHz FVCO 600MHz 3 200MHz FCLKOUT 600MHz 4 Don t set the P or M value as zero that is setting the P 000000 M 00000000 can cause malfunctio...

Page 232: ... When you set MPLL UPLL values you have to set the UPLL value first and then the MPLL value Needs intervals approximately 7 NOP PLL VALUE SELECTION TABLE It is not easy to find a proper PLL value So we recommend referring to the following PLL value recommendation table Input Frequency Output Frequency MDIV PDIV SDIV 12 0000MHz 48 00 MHz Note 80 8 1 12 0000MHz 96 00 MHz Note 80 8 0 12 0000MHz 300 0...

Page 233: ...Disable 1 Enable 1 UART2 12 Control PCLK into UART2 block 0 Disable 1 Enable 1 UART1 11 Control PCLK into UART1 block 0 Disable 1 Enable 1 UART0 10 Control PCLK into UART0 block 0 Disable 1 Enable 1 SDI 9 Control PCLK into SDI interface block 0 Disable 1 Enable 1 PWMTIMER 8 Control PCLK into PWMTIMER block 0 Disable 1 Enable 1 USB device 7 Control PCLK into USB device block 0 Disable 1 Enable 1 US...

Page 234: ...PLL lock time is inserted automatically 1 UCLK OFF UPLL is also turned off 0 Reserved 6 Reserved MPLL_OFF 5 0 Turn on PLL After PLL stabilization time minimum 300us SLOW_BIT can be cleared to 0 1 Turn off PLL PLL is turned off only when SLOW_BIT is 1 0 SLOW_BIT 4 0 FCLK Mpll MPLL output 1 SLOW mode FCLK input clock 2xSLOW_VAL when SLOW_VAL 0 FCLK input clock when SLOW_VAL 0 Input clock XTIpll or E...

Page 235: ...tate DIVN_UPLL 3 UCLK select register UCLK must be 48MHz for USB 0 UCLK UPLL clock 1 UCLK UPLL clock 2 Set to 0 when UPLL clock is set as 48Mhz Set to 1 when UPLL clock is set as 96Mhz 0 HDIVN 2 1 00 HCLK FCLK 1 01 HCLK FCLK 2 10 HCLK FCLK 4 when CAMDIVN 9 0 HCLK FCLK 8 when CAMDIVN 9 1 11 HCLK FCLK 3 when CAMDIVN 8 0 HCLK FCLK 6 when CAMDIVN 8 1 00 PDIVN 0 0 PCLK has the clock same as the HCLK 1 ...

Page 236: ...ate change bit when CLKDIVN 2 1 10b 0 HCLK FCLK 4 1 HCLK FCLK 8 Note1 Refer the CLKDIV register 0 HCLK3_HALF 8 HDIVN division rate change bit when CLKDIVN 2 1 11b 0 HCLK FCLK 3 1 HCLK FCLK 6Note1 Refer the CLKDIV register 0 CAM3CK_SEL 5 0 Enable divide factor setting register CMACLK_DIV 3 0 1 UPLL output 3 UPLL 3 is valid when CAMCLK_SEL 1 0 CAMCLK_SEL 4 0 Use CAMCLK with UPLL output CAMCLK UPLL o...

Page 237: ...hannel can handle the following four cases 1 Both source and destination are in the system bus 2 The source is in the system bus while the destination is in the peripheral bus 3 The source is in the peripheral bus while the destination is in the system bus 4 Both source and destination are in the peripheral bus The main advantage of the DMA is that it can transfer the data without CPU intervention...

Page 238: ...is cleared later State 3 In this state sub FSM which handles the atomic operation of DMA is initiated The sub FSM reads the data from the source address and then writes it to destination address In this operation data size and transfer size single or burst are considered This operation is repeated until the counter CURR_TC becomes 0 in Whole service mode while performed only once in Single service...

Page 239: ...g DMA operation which can make one DMA operation Figure 8 1 shows the basic Timing in the DMA operation of the SC32442B The setup time and the delay time of XnXDREQ and XnXDACK are the same in all the modes If the completion of XnXDREQ meets its setup time it is synchronized twice and then XnXDACK is asserted After assertion of XnXDACK DMA requests the bus and if it gets the bus it performs its op...

Page 240: ...ted the next transfer starts immediately Otherwise it waits for XnXDREQ to be asserted Handshake mode If XnXDREQ is de asserted DMA de asserts XnXDACK in 2cycles Otherwise it waits until XnXDREQ is de asserted Caution XnXDREQ has to be asserted low only after the de assertion high of XnXDACK Demand Mode XSCLK XnXDACK XnXDACK XnXDREQ XnXDREQ 2cycles Double synch Read Write Read Write Handshake Mode...

Page 241: ...the chunk of data Thus other bus masters cannot get the bus Burst 4 Transfer Size There will be four sequential Reads and Writes performed in the Burst 4 Transfer respectively Note Unit Transfer size One read and one write is performed XSCLK XnXDREQ XnXDACK Read Read Read Write Write Write Read Write 3 cycles Double synch Figure 8 3 Burst 4 Transfer Size ...

Page 242: ...XDACK XSCLK XnXDREQ XnXDACK Read Write Read Write Double synch Figure 8 4 Single service in Demand Mode with Unit Transfer Size Single service in Handshake Mode with Unit Transfer Size XnXDREQ XnXDACK XSCLK Read Write Read Write 2cycles Double synch Figure 8 5 Single service in Handshake Mode with Unit Transfer Size Whole service in Handshake Mode with Unit Transfer Size XSCLK XnXDREQ XnXDACK Read...

Page 243: ...nto CURR_SRC only if the CURR_SRC is 0 and the DMA ACK is 1 0x00000000 DMA INITIAL SOURCE CONTROL DISRCC REGISTER Register Address R W Description Reset Value DISRCC0 0x4B000004 R W DMA 0 initial source control register 0x00000000 DISRCC1 0x4B000044 R W DMA 1 initial source control register 0x00000000 DISRCC2 0x4B000084 R W DMA 2 initial source control register 0x00000000 DISRCC3 0x4B0000C4 R W DM...

Page 244: ...00000000 DIDSTC1 0x4B00004C R W DMA 1 initial destination control register 0x00000000 DIDSTC2 0x4B00008C R W DMA 2 initial destination control register 0x00000000 DIDSTC3 0x4B0000CC R W DMA 3 initial destination control register 0x00000000 DIDSTCn Bit Description Initial State CHK_INT 2 Select interrupt occurrence time when auto reload is setting 0 Interrupt will occur when TC reaches 0 1 Interrup...

Page 245: ...is de asserted It just de asserts DACK and then starts another transfer if DREQ is asserted We recommend using Handshake mode for external DMA request sources to prevent unintended starts of new transfers 0 SYNC 30 Select DREQ DACK synchronization 0 DREQ and DACK are synchronized to PCLK APB clock 1 DREQ and DACK are synchronized to HCLK AHB clock Therefore for devices attached to AHB system bus t...

Page 246: ...ect the DMA request source of each DMA These bits have meanings only if H W request mode is selected by DCONn 23 00 SWHW_SEL 23 Select the DMA source between software S W request mode and hardware H W request mode 0 S W request mode is selected and DMA is triggered by setting SW_TRIG bit of DMASKTRIG control register 1 DMA source selected by bit 26 24 triggers the DMA operation 0 RELOAD 22 Set the...

Page 247: ...r 000000h DSTAT3 0x4B0000D4 R DMA 3 count register 000000h DSTATn Bit Description Initial State STAT 21 20 Status of this DMA controller 00 Indicates that DMA controller is ready for another DMA request 01 Indicates that DMA controller is busy for transfers 00b CURR_TC 19 0 Current value of transfer count Note that transfer count is initially set to the value of DCONn 19 0 register and decreased b...

Page 248: ...r 0x00000000 DCSRCn Bit Description Initial State CURR_SRC 30 0 Current source address for DMAn 0x00000000 CURRENT DESTINATION DCDST REGISTER Register Address R W Description Reset Value DCDST0 0x4B00001C R DMA 0 current destination register 0x00000000 DCDST1 0x4B00005C R DMA 1 current destination register 0x00000000 DCDST2 0x4B00009C R DMA 2 current destination register 0x00000000 DCDST3 0x4B0000...

Page 249: ...annel is turned on and the DMA request is handled This bit is automatically set to off if we set the DCONn 22 bit to no auto reload and or STOP bit of DMASKTRIGn to stop Note that when DCON 22 bit is no auto reload this bit becomes 0 when CURR_TC reaches 0 If the STOP bit is 1 this bit becomes 0 as soon as the current atomic transfer is completed Note This bit should not be changed manually during...

Page 250: ...DMA SC32442B RISC MICROPROCESSOR 8 14 NOTES ...

Page 251: ... 16 input output port Port F GPF 8 input output port Port G GPG 16 input output port Port H GPH 9 input output port Port J GPJ 13 input output port Each port can be easily configured by software to meet various system configurations and design requirements You have to define which function of each pin is used before starting the main program If a pin is not used for multiplexed functions the pin c...

Page 252: ...ly ALE GPA17 Output only CLE GPA16 Output only nGCS5 GPA15 Output only nGCS4 GPA14 Output only nGCS3 GPA13 Output only nGCS2 GPA12 Output only nGCS1 GPA11 Output only ADDR26 GPA10 Output only ADDR25 GPA9 Output only ADDR24 GPA8 Output only ADDR23 GPA7 Output only ADDR22 GPA6 Output only ADDR21 GPA5 Output only ADDR20 GPA4 Output only ADDR19 GPA3 Output only ADDR18 GPA2 Output only ADDR17 GPA1 Outp...

Page 253: ...3 Input output TOUT3 GPB2 Input output TOUT2 GPB1 Input output TOUT1 GPB0 Input output TOUT0 Port C Selectable Pin Functions GPC15 Input output VD7 GPC14 Input output VD6 GPC13 Input output VD5 GPC12 Input output VD4 GPC11 Input output VD3 GPC10 Input output VD2 GPC9 Input output VD1 GPC8 Input output VD0 GPC7 Input output LCD_LPCREVB GPC6 Input output LCD_LPCREV GPC5 Input output LCD_LPCOE GPC4 I...

Page 254: ...14 GPD5 Input output VD13 GPD4 Input output VD12 GPD3 Input output VD11 GPD2 Input output VD10 GPD1 Input output VD9 SPICLK1 GPD0 Input output VD8 nSPICS1 Port E Selectable Pin Functions GPE15 Input output IICSDA GPE14 Input output IICSCL GPE13 Input output SPICLK0 GPE12 Input output SPIMOSI0 GPE11 Input output SPIMISO0 GPE10 Input output SDDAT3 GPE9 Input output SDDAT2 GPE8 Input output SDDAT1 GP...

Page 255: ...EINT0 Port G Selectable Pin Functions GPG15 Input output EINT23 GPG14 Input output EINT22 GPG13 Input output EINT21 GPG12 Input output EINT20 nSPICS0 GPG11 Input output EINT19 TCLK1 GPG10 Input output EINT18 nCTS1 GPG9 Input output EINT17 nRTS1 GPG8 Input output EINT16 GPG7 Input output EINT15 SPICLK1 GPG6 Input output EINT14 SPIMOSI1 GPG5 Input output EINT13 SPIMISO1 GPG4 Input output EINT12 LCD_...

Page 256: ...4 Input output TXD1 GPH3 Input output RXD0 GPH2 Input output TXD0 GPH1 Input output nRTS0 GPH0 Input output nCTS0 Port J Selectable Pin Functions GPJ12 Input output CAMRESET GPJ11 Input output CAMCLKOUT GPJ10 Input output CAMHREF GPJ9 Input output CAMVSYNC GPJ8 Input output CAMPCLK GPJ7 Input output CAMDATA7 GPJ6 Input output CAMDATA6 GPJ5 Input output CAMDATA5 GPJ4 Input output CAMDATA4 GPJ3 Inpu...

Page 257: ...own resister enable disable of each port group When the corresponding bit is 0 the pull down resister of the pin is enabled When 1 the pull down resister is disabled If the port pull down register is enabled then the pull down resisters work without pin s functional setting input output DATAn EINTn and etc MISCELLANEOUS CONTROL REGISTER This register controls DATA port pull down resister in Sleep ...

Page 258: ...tput 1 nRSTOUT GPA20 20 0 Output 1 nFRE GPA19 19 0 Output 1 nFWE GPA18 18 0 Output 1 ALE GPA17 17 0 Output 1 CLE GPA16 16 0 Output 1 nGCS 5 GPA15 15 0 Output 1 nGCS 4 GPA14 14 0 Output 1 nGCS 3 GPA13 13 0 Output 1 nGCS 2 GPA12 12 0 Output 1 nGCS 1 GPA11 11 0 Output 1 ADDR26 GPA10 10 0 Output 1 ADDR25 GPA9 9 0 Output 1 ADDR24 GPA8 8 0 Output 1 ADDR23 GPA7 7 0 Output 1 ADDR22 GPA6 6 0 Output 1 ADDR2...

Page 259: ...PADAT Bit Description GPA 24 0 24 0 When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read Note nRSTOUT nRESET nWDTRST SW_RESET ...

Page 260: ...0 Input 01 Output 10 nXBREQ 11 reserved GPB5 11 10 00 Input 01 Output 10 nXBACK 11 reserved GPB4 9 8 00 Input 01 Output 10 TCLK 0 11 reserved GPB3 7 6 00 Input 01 Output 10 TOUT3 11 reserved GPB2 5 4 00 Input 01 Output 10 TOUT2 11 reserved GPB1 3 2 00 Input 01 Output 10 TOUT1 11 reserved GPB0 1 0 00 Input 01 Output 10 TOUT0 11 reserved GPBDAT Bit Description GPB 10 0 10 0 When the port is configur...

Page 261: ...put 10 VD 5 11 Reserved GPC12 25 24 00 Input 01 Output 10 VD 4 11 Reserved GPC11 23 22 00 Input 01 Output 10 VD 3 11 Reserved GPC10 21 20 00 Input 01 Output 10 VD 2 11 Reserved GPC9 19 18 00 Input 01 Output 10 VD 1 11 Reserved GPC8 17 16 00 Input 01 Output 10 VD 0 11 Reserved GPC7 15 14 00 Input 01 Output 10 LCD_LPCREVB 11 Reserved GPC6 13 12 00 Input 01 Output 10 LCD_LPCREV 11 Reserved GPC5 11 10...

Page 262: ...it is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPCDN Bit Description GPC 15 0 15 0 0 the pull down function attached to to the corresponding port pin is enabled 1 the pull down function is disabled ...

Page 263: ...Output 10 VD 21 11 Reserved GPD12 25 24 00 Input 01 Output 10 VD 20 11 Reserved GPD11 23 22 00 Input 01 Output 10 VD 19 11 Reserved GPD10 21 20 00 Input 01 Output 10 VD 18 11 SPICLK1 GPD9 19 18 00 Input 01 Output 10 VD 17 11 SPIMOSI1 GPD8 17 16 00 Input 01 Output 10 VD 16 11 SPIMISO1 GPD7 15 14 00 Input 01 Output 10 VD 15 11 Reserved GPD6 13 12 00 Input 01 Output 10 VD 14 11 Reserved GPD5 11 10 00...

Page 264: ...it is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPDDN Bit Description GPD 15 0 15 0 0 the pull down function attached to to the corresponding port pin is enabled 1 the pull down function is disabled ...

Page 265: ...s no Pull down option GPE13 27 26 00 Input 01 Output 10 SPICLK0 11 Reserved GPE12 25 24 00 Input 01 Output 10 SPIMOSI0 11 Reserved GPE11 23 22 00 Input 01 Output 10 SPIMISO0 11 Reserved GPE10 21 20 00 Input 01 Output 10 SDDAT3 11 Reserved GPE9 19 18 00 Input 01 Output 10 SDDAT2 11 Reserved GPE8 17 16 00 Input 01 Output 10 SDDAT1 11 Reserved GPE7 15 14 00 Input 01 Output 10 SDDAT0 11 Reserved GPE6 ...

Page 266: ...t is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as a functional pin the undefined value will be read GPEDN Bit Description GPE 13 0 13 0 0 the pull down function attached to to the corresponding port pin is enabled 1 the pull down function is disabled ...

Page 267: ...eserved GPF5 11 10 00 Input 01 Output 10 EINT 5 11 Reserved GPF4 9 8 00 Input 01 Output 10 EINT 4 11 Reserved GPF3 7 6 00 Input 01 Output 10 EINT 3 11 Reserved GPF2 5 4 00 Input 01 Output 10 EINT2 11 Reserved GPF1 3 2 00 Input 01 Output 10 EINT 1 11 Reserved GPF0 1 0 00 Input 01 Output 10 EINT 0 11 Reserved GPFDAT Bit Description GPF 7 0 7 0 When the port is configured as an input port the corresp...

Page 268: ...ut 01 Output 10 EINT 21 11 Reserved GPG12 25 24 00 Input 01 Output 10 EINT 20 11 nSPICS0 GPG11 23 22 00 Input 01 Output 10 EINT 19 11 TCLK 1 GPG10 21 20 00 Input 01 Output 10 EINT 18 11 nCTS1 GPG9 19 18 00 Input 01 Output 10 EINT 17 11 nRTS1 GPG8 17 16 00 Input 01 Output 10 EINT 16 11 Reserved GPG7 15 14 00 Input 01 Output 10 EINT 15 11 SPICLK1 GPG6 13 12 00 Input 01 Output 10 EINT 14 11 SPIMOSI1 ...

Page 269: ...it is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPGDN Bit Description GPG 15 0 15 0 0 the pull down function attached to to the corresponding port pin is enabled 1 the pull down function is disabled ...

Page 270: ...GPH10 21 20 00 Input 01 Output 10 CLKOUT1 11 Reserved GPH9 19 18 00 Input 01 Output 10 CLKOUT0 11 nSPICS0 GPH8 17 16 00 Input 01 Output 10 UEXTCLK 11 Reserved GPH7 15 14 00 Input 01 Output 10 RXD 2 11 nCTS1 GPH6 13 12 00 Input 01 Output 10 TXD 2 11 nRTS1 GPH5 11 10 00 Input 01 Output 10 RXD 1 11 Reserved GPH4 9 8 00 Input 01 Output 10 TXD 1 11 Reserved GPH3 7 6 00 Input 01 Output 10 RXD 0 11 reser...

Page 271: ...it is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPHDN Bit Description GPH 10 0 10 0 0 the pull down function attached to to the corresponding port pin is enabled 1 the pull down function is disabled ...

Page 272: ... 01 Output 10 CAMCLKOUT 11 Reserved GPJ10 21 20 00 Input 01 Output 10 CAMHREF 11 Reserved GPJ9 19 18 00 Input 01 Output 10 CAMVSYNC 11 Reserved GPJ8 17 16 00 Input 01 Output 10 CAMPCLK 11 Reserved GPJ7 15 14 00 Input 01 Output 10 CAMDATA 7 11 Reserved GPJ6 13 12 00 Input 01 Output 10 CAMDATA 6 11 Reserved GPJ5 11 10 00 Input 01 Output 10 CAMDATA 5 11 Reserved GPJ4 9 8 00 Input 01 Output 10 CAMDATA...

Page 273: ...it is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPJDN Bit Description GPJ 12 0 12 0 0 the pull down function attached to to the corresponding port pin is enabled 1 the pull down function is disabled ...

Page 274: ...other values this bit is only for preventing from booting in Battery fault status 10X In sleep mode status when nBATT_FLT 0 the system will wake up In normal mode when nBATT_FLT 0 the Battery fault interrupt will occur 110 In sleep mode status during nBATT_FLT 0 the system will ignore all the wake up events the system will not wake up by wake up source In normal mode nBATT_FLT signal cannot affect...

Page 275: ... XTAL 001 UPLL output 010 FCLK 011 HCLK 100 PCLK 101 DCLK0 11x reserved 010 SEL_USBPAD 3 USB1 Host Device select register 0 use USB1 as Device 1 use USB1 as Host 0 Reserved 2 Reserved 0 SPUCR1 1 0 DATA 31 16 port pull down resister is enabled 1 DATA 31 16 port pull down resister is disabled 0 SPUCR0 0 0 DATA 15 0 port pull down resister is enabled 1 DATA 15 0 port pull down resister is disabled 0 ...

Page 276: ... n 1 DCLK1DIV 23 20 DCLK1 Divde value DCLK1 frequency source clock DCLK1DIV 1 DCLK1SelCK 17 Select DCLK1 source clock 0 PCLK 1 UCLK USB DCLK1EN 16 DCLK1 Enable 0 DCLK1 disable 1 DCLK1 enable DCLK0CMP 11 8 DCLK0 Compare value clock toggle value DCLK0DIV If the DCLK0CMP is n Low level duration is n 1 High level duration is DCLK0DIV 1 n 1 DCLK0DIV 7 4 DCLK0 Divde value DCLK0 frequency source clock DC...

Page 277: ...6 26 24 Setting the signaling method of the EINT6 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT5 22 20 Setting the signaling method of the EINT5 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT4 18 16 Setting the signaling method of the EINT4 000 Low level 001 High level 0...

Page 278: ...g the signaling method of the EINT12 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN11 15 Filter Enable for EINT11 0 Filter Disable 1 Filter Enable EINT11 14 12 Setting the signaling method of the EINT11 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN10 11 Filter Enable f...

Page 279: ... Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 FLTEN20 19 Filter Enable for EINT20 0 Filter Disable 1 Filter Enable 0 EINT20 18 16 Setting the signaling method of the EINT20 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 FLTEN19 15 Filter Enable for EINT19 0 Filter Disable 1 F...

Page 280: ... level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 FLTEN16 3 Filter Enable for EINT16 0 Filter Disable 1 Filter Enable 0 EINT16 2 0 Setting the signaling method of the EINT16 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 ...

Page 281: ...gured by OM 0 PCLK 1 EXTCLK OSC_CLK EINTFLT18 22 16 Filtering width of EINT18 FLTCLK17 15 Filter clock of EINT17 Configured by OM 0 PCLK 1 EXTCLK OSC_CLK EINTFLT17 14 8 Filtering width of EINT17 FLTCLK16 7 Filter clock of EINT16 Configured by OM 0 PCLK 1 EXTCLK OSC_CLK EINTFLT16 6 0 Filtering width of EINT16 EINTFLT3 Bit Description FLTCLK23 31 Filter clock of EINT23 Configured by OM 0 PCLK 1 EXTC...

Page 282: ...nterrupt 1 masked EINT18 18 0 enable interrupt 1 masked EINT17 17 0 enable interrupt 1 masked EINT16 16 0 enable interrupt 1 masked EINT15 15 0 enable interrupt 1 masked EINT14 14 0 enable interrupt 1 masked EINT13 13 0 enable interrupt 1 masked EINT12 12 0 enable interrupt 1 masked EINT11 11 0 enable interrupt 1 masked EINT10 10 0 enable interrupt 1 masked EINT9 9 0 enable interrupt 1 masked EINT...

Page 283: ... occur interrupt 0 EINT17 17 It is cleard by writing 1 0 not occur 1 occur interrupt 0 EINT16 16 It is cleard by writing 1 0 not occur 1 occur interrupt 0 EINT15 15 It is cleard by writing 1 0 not occur 1 occur interrupt 0 EINT14 14 It is cleard by writing 1 0 not occur 1 occur interrupt 0 EINT13 13 It is cleard by writing 1 0 not occur 1 occur interrupt 0 EINT12 12 It is cleard by writing 1 0 not...

Page 284: ...I O PORTS S3C2442B RISC MICROPROCESSOR 9 34 EINT5 5 It is cleard by writing 1 0 not occur 1 occur interrupt 0 EINT4 4 It is cleard by writing 1 0 not occur 1 occur interrupt 0 Reserved 3 0 Reserved 0000 ...

Page 285: ...nB pin BATT_FLT 0 Status of BATT_FLT pin GSTATUS1 Bit Description CHIP ID 0 ID register 0x32440aab GSTATUS2 Bit Description DeepSTOPRST 3 Boot is caused by Deep STOP mode cleared by writing 1 WDTRST 2 Boot is caused by Watch Dog Reset cleared by writing 1 SLEEPRST 1 Boot is caused by wakeup reset in sleep mode cleared by writing 1 PWRST 0 Boot is caused by Power On Reset cleared by writing 1 GSTAT...

Page 286: ...iption Reset Value nEN_DSC 31 enable Drive Strength Control 0 enable 1 Disable 0 Reserved 30 10 0 DSC_ADR 9 8 Address Bus Drive strength 00 12mA 10 10mA 01 8mA 11 6mA 00 DSC_DATA3 7 6 DATA 31 24 I O Drive strength 00 12mA 10 10mA 01 8mA 11 6mA 00 DSC_DATA2 5 4 DATA 23 16 I O Drive strength 00 12mA 10 10mA 01 8mA 11 6mA 00 DSC_DATA1 3 2 DATA 15 8 I O Drive strength 00 12mA 10 10mA 01 8mA 11 6mA 00 ...

Page 287: ...SC_BE 19 18 nBE 3 0 Drive strength 00 10mA 10 8mA 01 6mA 11 4mA 00 DSC_WOE 17 16 nWE nOE Drive strength 00 10mA 10 8mA 01 6mA 11 4mA 00 DSC_CS7 15 14 nGCS7 Drive strength 00 10mA 10 8mA 01 6mA 11 4mA 00 DSC_CS6 13 12 nGCS6 Drive strength 00 10mA 10 8mA 01 6mA 11 4mA 00 DSC_CS5 11 10 nGCS5 Drive strength 00 10mA 10 8mA 01 6mA 11 4mA 00 DSC_CS4 9 8 nGCS4 Drive strength 00 10mA 10 8mA 01 6mA 11 4mA 0...

Page 288: ...put 0 0 PSC_NF 8 NAND Flash I F pin status in Sleep mode nFCE nFRE nFWE ALE CLE 0 inactive nFCE nFRE nFWE ALE CLE 11100 1 Hi Z 0 PSC_SDR 7 nSRAS nSCAS pin status in Sleep mode 0 inactive 1 1 Hi Z 0 PSC_DQM 6 DQM 3 0 nWE 3 0 pin status in Sleep mode 0 inactive 1 Hi Z 0 PSC_OE 5 nOE pin status in Sleep mode 0 inactive 1 1 Hi Z 0 PSC_WE 4 nWE pin status in Sleep mode 0 inactive 1 1 Hi Z 0 PSC_GCS0 3 ...

Page 289: ...ter to be compared with the down counter value This double buffering feature of TCNTBn and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed Each timer has its own 16 bit down counter which is driven by the timer clock When the down counter reaches zero the timer interrupt request is generated to inform the CPU that the timer operation has been completed...

Page 290: ...PB0 TCNTB0 Control Logic1 TCMPB1 TCNTB1 5 1 MUX Clock Divider 5 1 MUX 5 1 MUX Control Logic2 TCMPB2 TCNTB2 TOUT3 Control Logic3 TCMPB3 TCNTB3 No Pin PCLK 8 Bit Prescaler 8 Bit Prescaler Dead Zone Dead Zone TCLK0 1 8 1 4 1 16 1 2 TCLK1 1 8 1 4 1 16 1 2 5 1 MUX Control Logic4 TCNTB4 Figure 10 1 16 bit PWM Timer Block Diagram ...

Page 291: ...50 MHz 81 9188 us 12 2070 KHz 5 3686 sec BASIC TIMER OPERATION TCMPn 1 0 TCNTn 3 3 2 1 0 2 1 0 0 Start bit 1 Timer is started TCNTn TCMPn Auto reload TCNTn TCMPn Timer is stopped TOUTn Command Status TCNTBn 3 TCMPBn 1 Manual update 1 Auto reload 1 TCNTBn 2 TCMPBn 0 Manual update 0 Auto reload 1 Interrupt request Auto reload Interrupt request Figure 10 2 Timer Operations A timer except the timer ch...

Page 292: ...f the timer can be read from Timer Count Observation register TCNTOn If the TCNTBn is read the read value does not indicate the current state of the counter but the reload value for the next timer duration The auto reload operation copies the TCNTBn into TCNTn when the TCNTn reaches 0 The value written into the TCNTBn is loaded to the TCNTn only when the TCNTn reaches 0 and auto reload is enabled ...

Page 293: ...TBn and TCMPBn 2 Set the manual update bit of the corresponding timer It is recommended that you configure the inverter on off bit Whether use inverter or not 3 Set start bit of the corresponding timer to start the timer and clear the manual update bit If the timer is stopped by force the TCNTn retains the counter value and is not reloaded from TCNTBn If a new value has to be set perform manual up...

Page 294: ... the TCMPn the logic level of the TOUTn is changed from low to high 4 When the TCNTn reaches 0 the interrupt request is generated and TCNTBn value is loaded into a temporary register At the next timer tick the TCNTn is reloaded with the temporary register value TCNTBn 5 In Interrupt Service Routine ISR the TCNTBn and the TCMPBn are set to 80 20 60 and 60 respectively for the next duration 6 When t...

Page 295: ...an be implemented by using the TCMPBn PWM frequency is determined by TCNTBn Figure 10 5 shows a PWM value determined by TCMPBn For a higher PWM value decrease the TCMPBn value For a lower PWM value increase the TCMPBn value If an output inverter is enabled the increment decrement may be reversed The double buffering function allows the TCMPBn for the next PWM cycle written at any point in the curr...

Page 296: ...ow assume the inverter is off 1 Turn off the auto reload bit And then TOUTn goes to high level and the timer is stopped after the TCNTn reaches 0 recommended 2 Stop the timer by clearing the timer start stop bit to 0 If TCNTn TCMPn the output level is high If TCNTn TCMPn the output level is low 3 The TOUTn can be inverted by the inverter on off bit in TCON The inverter removes the additional circu...

Page 297: ...witching devices from being turned on simultaneously even for a very short time TOUT0 is the PWM output nTOUT0 is the inversion of the TOUT0 If the dead zone is enabled the output wave form of TOUT0 and nTOUT0 will be TOUT0_DZ and nTOUT0_DZ respectively nTOUT0_DZ is routed to the TOUT1 pin In the dead zone interval TOUT0_DZ and nTOUT0_DZ can never be turned on simultaneously TOUT0 nTOUT0 TOUT0_DZ ...

Page 298: ...TCFG1 register If one of timers is configured as DMA request mode that timer does not generate an interrupt request The others can generate interrupt normally DMA mode configuration and DMA interrupt operation DMA Mode DMA Request Timer0 INT Timer1 INT Timer2 INT Timer3 INT Timer4 INT 0000 No select ON ON ON ON ON 0001 Timer0 OFF ON ON ON ON 0010 Timer1 ON OFF ON ON ON 0011 Timer2 ON ON OFF ON ON ...

Page 299: ...scription Reset Value TCFG0 0x51000000 R W Configures the two 8 bit prescalers 0x00000000 TCFG0 Bit Description Initial State Reserved 31 24 0x00 Dead zone length 23 16 These 8 bits determine the dead zone length The 1 unit time of the dead zone length is equal to that of timer 0 0x00 Prescaler 1 15 8 These 8 bits determine prescaler value for Timer 2 3 and 4 0x00 Prescaler 0 7 0 These 8 bits dete...

Page 300: ... Timer3 0101 Timer4 0110 Reserved 0000 MUX 4 19 16 Select MUX input for PWM Timer4 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK1 0000 MUX 3 15 12 Select MUX input for PWM Timer3 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK1 0000 MUX 2 11 8 Select MUX input for PWM Timer2 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK1 0000 MUX 1 7 4 Select MUX input for PWM Timer1 00...

Page 301: ...ion 1 Update TCNTB3 TCMPB3 0 Timer 3 start stop 16 Determine start stop for Timer 3 0 Stop 1 Start for Timer 3 0 Timer 2 auto reload on off 15 Determine auto reload on off for Timer 2 0 One shot 1 Interval mode auto reload 0 Timer 2 output inverter on off 14 Determine output inverter on off for Timer 2 0 Inverter off 1 Inverter on for TOUT2 0 Timer 2 manual update note 13 Determine the manual upda...

Page 302: ...uto reload on off for Timer 0 0 One shot 1 Interval mode auto reload 0 Timer 0 output inverter on off 2 Determine the output inverter on off for Timer 0 0 Inverter off 1 Inverter on for TOUT0 0 Timer 0 manual update note 1 Determine the manual update for Timer 0 0 No operation 1 Update TCNTB0 TCMPB0 0 Timer 0 start stop 0 Determine start stop for Timer 0 0 Stop 1 Start for Timer 0 0 NOTE The bit h...

Page 303: ...scription Initial State Timer 0 compare buffer register 15 0 Set compare buffer value for Timer 0 0x00000000 TCNTB0 Bit Description Initial State Timer 0 count buffer register 15 0 Set count buffer value for Timer 0 0x00000000 TIMER 0 COUNT OBSERVATION REGISTER TCNTO0 Register Address R W Description Reset Value TCNTO0 0x51000014 R Timer 0 count observation register 0x00000000 TCNTO0 Bit Descripti...

Page 304: ...scription Initial State Timer 1 compare buffer register 15 0 Set compare buffer value for Timer 1 0x00000000 TCNTB1 Bit Description Initial State Timer 1 count buffer register 15 0 Set count buffer value for Timer 1 0x00000000 TIMER 1 COUNT OBSERVATION REGISTER TCNTO1 Register Address R W Description Reset Value TCNTO1 0x51000020 R Timer 1 count observation register 0x00000000 TCNTO1 Bit Descripti...

Page 305: ...scription Initial State Timer 2 compare buffer register 15 0 Set compare buffer value for Timer 2 0x00000000 TCNTB2 Bit Description Initial State Timer 2 count buffer register 15 0 Set count buffer value for Timer 2 0x00000000 TIMER 2 COUNT OBSERVATION REGISTER TCNTO2 Register Address R W Description Reset Value TCNTO2 0x5100002C R Timer 2 count observation register 0x00000000 TCNTO2 Bit Descripti...

Page 306: ...scription Initial State Timer 3 compare buffer register 15 0 Set compare buffer value for Timer 3 0x00000000 TCNTB3 Bit Description Initial State Timer 3 count buffer register 15 0 Set count buffer value for Timer 3 0x00000000 TIMER 3 COUNT OBSERVATION REGISTER TCNTO3 Register Address R W Description Reset Value TCNTO3 0x51000038 R Timer 3 count observation register 0x00000000 TCNTO3 Bit Descripti...

Page 307: ...TCNTB4 Bit Description Initial State Timer 4 count buffer register 15 0 Set count buffer value for Timer 4 0x00000000 TIMER 4 COUNT OBSERVATION REGISTER TCNTO4 Register Address R W Description Reset Value TCNTO4 0x51000040 R Timer 4 count observation register 0x00000000 TCNTO4 Bit Description Initial State Timer 4 observation register 15 0 Set count observation value for Timer 4 0x00000000 ...

Page 308: ...PWM TIMER SC32442B RISC MICROPROCESSOR 10 20 NOTES ...

Page 309: ...red IR transmit receive one or two stop bit insertion 5 bit 6 bit 7 bit or 8 bit data width and parity checking Each UART contains a baud rate generator transmitter receiver and a control unit as shown in Figure 11 1 The baud rate generator can be clocked by PCLK FCLK n or UEXTCLK external input clock The transmitter and the receiver contain 64 byte FIFOs and data shifters Data is written to FIFO ...

Page 310: ... F IF O m o d e R e c e iv e F IF O R e g is te r F IF O m o d e R e c e iv e H o ld in g R e g is te r N o n F IF O m o d e o n ly In F IF O m o d e a ll 6 4 B y te o f B u ffe r re g is te r a re u s e d a s F IF O re g is te r In n o n F IF O m o d e o n ly 1 B y te o f B u ffe r re g is te r is u s e d a s H o ld in g re g is te r T ra n s m it S h ifte r T ra n s m it B u ffe r R e g is te r ...

Page 311: ... holding register in the case of Non FIFO mode Data Reception Like the transmission the data frame for reception is also programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits in the line control register ULCONn The receiver can detect overrun error parity error frame error and break condition each of which can set an error flag The overrun error indic...

Page 312: ...vated when its receive FIFO has a spare under 32 byte in AFC nRTS means that its own receive FIFO is ready to receive data RxD nRTS UART A TxD nCTS UART B TxD nCTS UART A RxD nRTS UART B Transmission case in UART A Reception case in UART A Figure 11 2 UART AFC interface NOTE UART 2 does not support AFC function because the SC32442B has no nRTS2 and nCTS2 Example of Non Auto Flow control controllin...

Page 313: ...ill cause Rx interrupt under the Interrupt request and polling mode When the transmitter transfers data from its transmit FIFO register to its transmit shifter and the number of data left in transmit FIFO reaches Tx FIFO Trigger Level Tx interrupt is generated if Transmit mode in control register is selected as Interrupt request or polling mode In the Non FIFO mode transferring data from the trans...

Page 314: ... receive error will not generate any error interrupt because the character which is received with an error would have not been read The error interrupt will occur once the character is read Figure 11 3 shows the UART receiving the five characters including the two errors Time Sequence Flow Error Interrupt Note 0 When no character is read out 1 A B C D and E is received 2 After A is read out The fr...

Page 315: ...is 40 MHz UBRDIVn is UBRDIVn int 40000000 115200 x 16 1 int 21 7 1 round to the nearest whole number 22 1 21 Baud Rate Error Tolerance UART Frame error should be less than 1 87 3 160 tUPCLK UBRDIVn 1 x 16 x 1Frame PCLK tUPCLK Real UART Clock tUEXACT 1Frame baud rate tUEXACT Ideal UART Clock UART error tUPCLK tUEXACT tUEXACT x 100 NOTE 1 1Frame start bit data bit parity bit stop bit 2 In specific c...

Page 316: ...lustrates how to implement the IR mode In IR transmit mode the transmit pulse comes out at a rate of 3 16 the normal serial transmit rate when the transmit data bit is zero In IR receive mode the receiver must detect the 3 16 pulsed period to recognize a zero value see the frame timing diagrams shown in Figure 11 6 and 11 7 IrDA Tx Encoder 0 1 0 1 IrDA Rx Decoder TxD RxD TxD IRS RxD RE UART Block ...

Page 317: ... I O Frame Timing Diagram Normal UART 0 Start Bit Stop Bit Data Bits IR Transmit Frame Bit Time Pulse Width 3 16 Bit Frame 0 0 0 0 1 1 1 1 1 Figure 11 5 Infrared Transmit Mode Frame Timing Diagram 0 Start Bit Stop Bit Data Bits IR Receive Frame 0 0 0 0 1 1 1 1 1 Figure 11 6 Infrared Receive Mode Frame Timing Diagram ...

Page 318: ...ription Initial State Reserved 7 0 Infrared Mode 6 Determine whether or not to use the Infrared mode 0 Normal mode operation 1 Infrared Tx Rx mode 0 Parity Mode 5 3 Specify the type of parity generation and checking during UART transmit and receive operation 0xx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked as 0 000 Number of Stop Bit 2 Specify h...

Page 319: ... FCLK n clock 1 Enable FCLK n clock In case of UCON0 UART clock FCLK divider 6 where divider 0 UCON1 UCON2 must be zero ex 1 UART clock FCLK 7 2 UART clock FCLK 8 3 UART clock FCLK 9 15 UART clock FCLK 21 In case of UCON1 UART clock FCLK divider 21 where divider 0 UCON0 UCON2 must be zero ex 1 UART clock FCLK 22 2 UART clock FCLK 23 3 UART clock FCLK 24 15 UART clock FCLK 36 In case of UCON2 UART ...

Page 320: ... when UART FIFO is enabled The interrupt is a receive interrupt 0 Disable 1 Enable 0 Rx Error Status Interrupt Enable 6 Enable the UART to generate an interrupt upon an exception such as a break frame error parity error or overrun error during a receive operation 0 Do not generate receive error status interrupt 1 Generate receive error status interrupt 0 Loopback Mode 5 Setting loopback bit to 1 c...

Page 321: ...nly for UART1 00 Receive Mode 1 0 Determine which function is currently able to read data from UART receive buffer register UART Rx Enable Disable 00 Disable 01 Interrupt request or polling mode 10 DMA0 request Only for UART0 DMA3 request Only for UART2 11 DMA1 request Only for UART1 00 Note When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA rec...

Page 322: ...7 6 Determine the trigger level of transmit FIFO 00 Empty 01 16 byte 10 32 byte 11 48 byte 00 Rx FIFO Trigger Level 5 4 Determine the trigger level of receive FIFO 00 1 byte 01 8 byte 10 16 byte 11 32 byte 00 Reserved 3 0 Tx FIFO Reset 2 Auto cleared after resetting FIFO 0 Normal 1 Tx FIFO reset 0 Rx FIFO Reset 1 Auto cleared after resetting FIFO 0 Normal 1 Rx FIFO reset 0 FIFO Enable 0 0 Disable ...

Page 323: ...ter 0x0 Reserved 0x5000800C Reserved Undef UMCONn Bit Description Initial State Reserved 7 5 These bits must be 0 s 00 Auto Flow Control AFC 4 0 Disable 1 Enable 0 Reserved 3 1 These bits must be 0 s 00 Request to Send 0 If AFC bit is enabled this value will be ignored In this case the SC32442B will control nRTS automatically If AFC bit is disabled nRTS must be controlled by software 0 H level Ina...

Page 324: ...Transmitter transmit buffer shifter register empty 1 Transmit buffer empty 1 Set to 1 automatically when transmit buffer register is empty 0 The buffer register is not empty 1 Empty In Non FIFO mode Interrupt or DMA is requested In FIFO mode Interrupt or DMA is requested when Tx FIFO Trigger Level is set to 00 Empty If the UART uses the FIFO users should check Tx FIFO Count bits and Tx FIFO Full b...

Page 325: ...e that a break signal has been received 0 No break receive 1 Break receive Interrupt is requested 0 Frame Error 2 Set to 1 automatically whenever a frame error occurs during receive operation 0 No frame error during receive 1 Frame error Interrupt is requested 0 Parity Error 1 Set to 1 automatically whenever a parity error occurs during receive operation 0 No parity error during receive 1 Parity e...

Page 326: ...IFO status register 0x00 UFSTAT2 0x50008018 R UART channel 2 FIFO status register 0x00 UFSTATn Bit Description Initial State Reserved 15 0 Tx FIFO Full 14 Set to 1 automatically whenever transmit FIFO is full during transmit operation 0 0 byte Tx FIFO data 63 byte 1 Full 0 Tx FIFO Count 13 8 Number of data in Tx FIFO 0 Reserved 7 0 Rx FIFO Full 6 Set to 1 automatically whenever receive FIFO is ful...

Page 327: ... R UART channel 1 Modem status register 0x0 Reserved 0x5000801C Reserved Undef UMSTAT0 Bit Description Initial State Delta CTS 4 Indicate that the nCTS input to the SC32442B has changed state since the last time it was read by CPU Refer to Figure 11 8 0 Has not changed 1 Has changed 0 Reserved 3 1 0 Clear to Send 0 0 CTS signal is not activated nCTS pin is high 1 CTS signal is activated nCTS pin i...

Page 328: ...n Note L The endian mode is Little endian B The endian mode is Big endian UART RECEIVE BUFFER REGISTER HOLDING REGISTER FIFO REGISTER There are three UART receive buffer registers including URXH0 URXH1 and URXH2 in the UART block URXHn has an 8 bit data for received data Register Address R W Description Reset Value URXH0 0x50000024 L 0x50000027 B R by byte UART channel 0 receive buffer register UR...

Page 329: ... from 1 to 216 1 but can be set zero only using the UEXTCLK which should be smaller than PCLK For example if the baud rate is 115200 bps and UART clock is 40 MHz UBRDIVn is UBRDIVn int 40000000 115200 x 16 1 int 21 7 1 round to the nearest whole number 22 1 21 Register Address R W Description Reset Value UBRDIV0 0x50000028 R W Baud rate divisior register 0 UBRDIV1 0x50004028 R W Baud rate divisior...

Page 330: ...UART SC32442B RISC MICROPROCESSOR 11 22 NOTES ...

Page 331: ...DATA 32 HCI_DATA 32 CONTROL CONTROL OHCI REGS USB STATE CONTROL LIST PROCESSOR BLOCK ED TD REGS Cntl HCI MASTER BLOCK CONTROL ED TD_DATA 32 ED TD STATUS 32 64x8 FIFO Cntl HC_DATA 8 DF_DATA 8 APP_MDATA 32 HCM_ADR DATA 32 CONTROL STATUS CONTROL CTRL CTRL RH_DATA 8 DF_DATA 8 HCF_DATA 8 Addr 6 FIFO_DATA 8 64x8 FIFO ROOT HUB HOST SIE HSIE S M DPLL ROOT HUB HOST SIE OHCI ROOT HUB REGS PORT S M PORT S M ...

Page 332: ...onStatus 0x49000008 HcInterruptStatus 0x4900000C HcInterruptEnable 0x49000010 HcInterruptDisable 0x49000014 HcHCCA 0x49000018 Memory pointer group HcPeriodCuttentED 0x4900001C HcControlHeadED 0x49000020 HcControlCurrentED 0x49000024 HcBulkHeadED 0x49000028 HcBulkCurrentED 0x4900002C HcDoneHead 0x49000030 HcRmInterval 0x49000034 Frame counter group HcFmRemaining 0x49000038 HcFmNumber 0x4900003C HcP...

Page 333: ... interrupt or DMA EP2 128byte IN OUT FIFO dual port asynchronous RAM interrupt or DMA EP3 128byte IN OUT FIFO dual port asynchronous RAM interrupt or DMA EP4 128byte IN OUT FIFO dual port asynchronous RAM interrupt or DMA Integrated USB Transceiver FEATURE Fully compliant with USB Specification Version 1 1 Full speed 12Mbps device Integrated USB Transceiver Supports control interrupt and bulk tran...

Page 334: ...P_OUT RT_VM_IN RT_VP_IN RXD RT_UXSUSPEND RT_UX_OEN RT_VM_OUT MC_ADDR 13 0 SIU GFI FIFOs MCU DMA I F MC_DATA_IN 31 0 MC_DATA_OUT 31 0 USB_CLK SYS_CLK SYS_RESETN MC_WR WR_RDN MC_CSN MC_INTR DREQN 3 0 DACKN 3 0 Figure 13 1 USB Device Controller Block Diagram ...

Page 335: ...er 0x148 L 0x14B B USB_INT_REG USB interrupt register 0x158 L 0x15B B EP_INT_EN_REG EP0 EP4 Endpoint interrupt enable register 0x15C L 0x15F B USB_INT_EN_REG USB Interrupt enable register 0x16C L 0x16F B FRAME_NUM1_REG Frame number 1 register 0x170 L 0x173 B FRAME_NUM2_REG Frame number 2 register 0x174 L 0x177 B INDEX_REG Index register 0x178 L 0x17B B EP0_FIFO_REG Endpoint0 FIFO register 0x1C0 L ...

Page 336: ...A_TTC_H Endpoint3 DMA transfer counter high byte register 0x254 L 0x247 B EP4_DMA_CON Endpoint4 DMA control register 0x258 L 0x25B B EP4_DMA_UNIT Endpoint4 DMA unit counter register 0x25C L 0x25F B EP4_DMA_FIFO Endpoint4 DMA FIFO counter register 0x260 L 0x263 B EP4_DMA_TTC_L Endpoint4 DMA transfer counter low byte register 0x264 L 0x267 B EP4_DMA_TTC_M Endpoint4 DMA transfer counter middle byte r...

Page 337: ...ddress is used for the next token Register Address R W Description Reset Value FUNC_ADDR_REG 0x52000140 L 0x52000143 B R W byte Function address register 0x00 FUNC_ADDR_RE G Bit MCU USB Description Initial State ADDR_UPDATE 7 R SET R CLEAR Set by the MCU whenever it updates the FUNCTION_ADDR field in this register This bit will be cleared by USB when DATA_END bit in EP0_CSR register 0 FUNCTION_ADD...

Page 338: ...bit remains set as long as reset signaling persists on the bus 0 MCU_RESUME 2 R W R CLEAR Set by the MCU for MCU Resume The USB generates the resume signaling during 10ms if this bit is set in suspend mode SUSPEND_MODE 1 R SET CLEAR Set by USB automatically when the device enter into suspend mode It is cleared under the following conditions 1 The MCU clears the MCU_RESUME bit by writing 0 in order...

Page 339: ...200014B B R W byte EP interrupt pending clear register 0x00 EP_INT_REG Bit MCU USB Description Initial State EP1 EP4 Interrupt 4 1 R CLEAR SET For BULK INTERRUPT IN endpoints Set by the USB under the following conditions 1 IN_PKT_RDY bit is cleared 2 FIFO is flushed 3 SENT_STALL set For BULK INTERRUPT OUT endpoints Set by the USB under the following conditions 1 Sets OUT_PKT_RDY bit 2 Sets SENT_ST...

Page 340: ...gnaling while in Suspend mode If the resume occurs due to a USB reset then the MCU is first interrupted with a RESUME interrupt Once the clocks resume and the SE0 condition persists for 3ms USB RESET interrupt will be asserted 0 SUSPEND Interrupt 0 R CLEAR SET Set by the USB when it receives suspend signalizing This bit is set whenever there is no activity for 3ms on the bus Thus if the MCU does n...

Page 341: ...er Address R W Description Reset Value EP_INT_EN_REG 0x5200015C L 0x5200015F B R W byte Determine which interrupt is enabled 0xFF EP_INT_EN_REG Bit MCU USB Description Initial State EP4_INT_EN 4 R W R EP4 Interrupt Enable bit 0 Interrupt disable 1 Enable 1 EP3_INT_EN 3 R W R EP3 Interrupt Enable bit 0 Interrupt disable 1 Enable 1 EP2_INT_EN 2 R W R EP2 Interrupt Enable bit 0 Interrupt disable 1 En...

Page 342: ...EG 0x520016C L 0x5200016F B R W byte Determine which interrupt is enabled 0x04 INT_MASK_REG Bit MCU USB Description Initial State RESET_INT_EN 2 R W R Reset interrupt enable bit 0 Interrupt disable 1 Enable 1 Reserved 1 0 SUSPEND_INT_EN 0 R W R Suspend interrupt enable bit 0 Interrupt disable 1 Enable 0 ...

Page 343: ...atically Register Address R W Description Reset Value FRAME_NUM1_REG 0x52000170 L 0x52000173 B R byte Frame number lower byte register 0x00 FRAME_NUM_REG Bit MCU USB Description Initial State FRAME_NUM1 7 0 R W Frame number lower byte value 00 Register Address R W Description Reset Value FRAME_NUM2_REG 0x52000174 L 0x52000177 B R byte Frame number higher byte register 0x00 FRAME_NUM_REG Bit MCU US...

Page 344: ...X_REG 0x52000178 L 0x5200017B B R W byte Register index register 0x00 INDEX_REG Bit MCU USB Description Initial State INDEX 7 0 R W R Indicate a certain endpoint 00 MAX PACKET REGISTER MAXP_REG Register Address R W Description Reset Value MAXP_REG 0x52000180 L 0x52000183 B R W byte End Point MAX packet register 0x01 MAXP_REG Bit MCU USB Description Initial State MAXP 3 0 R W R 0000 Reserved 0001 M...

Page 345: ...ntrol transfer ends before DATA_END is set When the USB sets this bit an interrupt is generated to the MCU When such a condition occurs the USB flushes the FIFO and invalidates MCU access to the FIFO 0 DATA_END 3 SET CLEAR Set by the MCU on the conditions below 1 After loading the last packet of data into the FIFO at the same time IN_PKT_RDY is set 2 While it clears OUT_PKT_RDY after unloading the...

Page 346: ...it to finish the STALL condition 1 The MCU issues a STALL handshake to the USB 0 FIFO_FLUSH 3 R W CLEAR Set by the MCU if it intends to flush the packet in Input related FIFO This bit is cleared by the USB when the FIFO is flushed The MCU is interrupted when this happens If a token is in process the USB waits until the transmission is complete before FIFO flushing If two packets are loaded into th...

Page 347: ... from MCU If the MCU writes less than MAXP data IN_PKT_RDY bit has to be set by the MCU 0 ISO 6 R W R Used only for endpoints whose transfer type is programmable 1 Reserved 0 Configures endpoint to Bulk mode 0 MODE_IN 5 R W R Used only for endpoints whose direction is programmable 1 Configures Endpoint Direction as IN 0 Configures Endpoint Direction as OUT 1 IN_DMA_INT_EN 4 R W R Determine whether...

Page 348: ...ake The USB issues a stall handshake to the host if it sends more than MAXP data for the OUT TOKEN 0 SEND_STALL 5 R W R 0 The MCU clears this bit to end the STALL condition handshake IN PKT RDY is cleared 1 The MCU issues a STALL handshake to the USB The MCU clears this bit to end the STALL condition handshake IN PKT RDY is cleared 0 FIFO_FLUSH 4 R W CLEAR The MCU writes a 1 to flush the FIFO This...

Page 349: ...7 R W R If the MCU is set whenever the MCU reads data from the OUT FIFO OUT_PKT_RDY will automatically be cleared by the logic without any intervention from the MCU 0 ISO 6 R W R Determine endpoint transfer type 0 Configures endpoint to Bulk mode 1 Reserved 0 OUT_DMA_INT_MAS K 5 R W R Determine whether the interrupt should be issued or not OUT_PKT_RDY condition happens This is only useful for DMA ...

Page 350: ... count register2 0x00 OUT_FIFO_CNT2_REG Bit MCU USB Description Initial State OUT_CNT_HIGH 7 0 R W Higher byte of write count The OUT_CNT_HIGH may be always 0 normally 0x00 END POINT FIFO REGISTER EPN_FIFO_REG The EPn_FIFO_REG enables the MCU to access to the EPn FIFO Register Address R W Description Reset Value EP0_FIFO 0x520001C0 L 0x520001C3 B R W byte End Point0 FIFO register 0xXX EP1_FIFO 0x5...

Page 351: ... 7 R W W Read DMA Run Observation 0 DMA is stopped 1 DMA is running Write Ignore EPn_DMA_TTC_n register 0 DMA requests will be stopped if EPn_DMA_TTC_n reaches 0 1 DMA requests will be continued although EPn_DMA_TTC_n reaches 0 0 STATE 6 4 R W DMA State Monitoring 0 DEMAND_MODE 3 R W R DMA Demand mode enable bit 0 Demand mode disable 1 Demand mode enable 0 OUT_RUN_OB OUT_DMA_RUN 2 R W R W Function...

Page 352: ... B R W byte EP1 DMA transfer unit counter base register 0x00 EP2_DMA_UNIT 0x5200021C L 0x5200021F B R W byte EP2 DMA transfer unit counter base register 0x00 EP3_DMA_UNIT 0x52000244 L 0x52000247 B R W byte EP3 DMA transfer unit counter base register 0x00 EP4_DMA_UNIT 0x5200025C L 0x5200025F B R W byte EP4 DMA transfer unit counter base register 0x00 DMA_UNIT Bit MCU USB Description Initial State E...

Page 353: ...e Register Address R W Description Reset Value EP1_DMA_FIFO 0x52000208 L 0x5200020B B R W byte EP1 DMA transfer FIFO counter base register 0x00 EP2_DMA_FIFO 0x52000220 L 0x52000223 B R W byte EP2 DMA transfer FIFO counter base register 0x00 EP3_DMA_FIFO 0x52000248 L 0x5200024B B R W byte EP3 DMA transfer FIFO counter base register 0x00 EP4_DMA_FIFO 0x52000260 L 0x52000263 B R W byte EP4 DMA transf...

Page 354: ... EP2_DMA_TTC_H 0x5200022C L 0x5200022F B R W byte EP2 DMA total transfer counter higher byte 0x00 EP3_DMA_TTC_L 0x5200024C L 0x5200024F B R W byte EP3 DMA total transfer counter lower byte 0x00 EP3_DMA_TTC_M 0x52000250 L 0x52000253 B R W byte EP3 DMA total transfer counter middle byte 0x00 EP3_DMA_TTC_H 0x52000254 L 0x52000257 B R W byte EP3 DMA total transfer counter higher byte 0x00 EP4_DMA_TTC_...

Page 355: ...internal peripherals and external interrupt request pins the interrupt controller requests FIQ or IRQ interrupt of the ARM920T core after the arbitration procedure The arbitration procedure depends on the hardware priority logic and the result is written to the interrupt pending register which helps users notify which interrupt is generated out of various interrupt sources Request sources with sub...

Page 356: ...pending or not When the interrupt sources request interrupt the service the corresponding bits of SRCPND register are set to 1 and at the same time only one bit of the INTPND register is set to 1 automatically after arbitration procedure If interrupts are masked then the corresponding bits of the SRCPND register are set to 1 This does not cause the bit of INTPND register changed When a pending bit...

Page 357: ...upt ARB 3 INT_DMA3 DMA channel 3 interrupt ARB3 INT_DMA2 DMA channel 2 interrupt ARB3 INT_DMA1 DMA channel 1 interrupt ARB3 INT_DMA0 DMA channel 0 interrupt ARB3 INT_LCD LCD interrupt INT_FrSyn and INT_FiCnt ARB3 INT_UART2 UART2 Interrupt ERR RXD and TXD ARB2 INT_TIMER4 Timer4 interrupt ARB2 INT_TIMER3 Timer3 interrupt ARB2 INT_TIMER2 Timer2 interrupt ARB2 INT_TIMER1 Timer1 interrupt ARB 2 INT_TIM...

Page 358: ...interrupt INT_ADC INT_TC Touch screen interrupt pen up down INT_ADC INT_ERR2 UART2 error interrupt INT_UART2 INT_TXD2 UART2 transmit interrupt INT_UART2 INT_RXD2 UART2 receive interrupt INT_UART2 INT_ERR1 UART1 error interrupt INT_UART1 INT_TXD1 UART1 transmit interrupt INT_UART1 INT_RXD1 UART1 receive interrupt INT_UART1 INT_ERR0 UART0 error interrupt INT_UART0 INT_TXD0 UART0 transmit interrupt I...

Page 359: ...BITER3 ARBITER4 ARBITER5 REQ4 INT_TICK REQ5 INT_WDT REQ0 INT_TIMER0 REQ3 INT_TIMER3 REQ2 INT_TIMER2 REQ1 INT_TIMER1 REQ4 INT_TIMER4 REQ0 INT_LCD REQ1 INT_DMA0 REQ3 INT_DMA2 REQ2 INT_DMA1 REQ5 INT_UART2 REQ4 INT_DMA3 REQ5 INT_SDI REQ0 INT_SPI0 REQ1 INT_UART1 REQ2 INT_NFCON REQ3 INT_USBD REQ4 INT_USBH REQ5 INT_IIC REQ1 INT_UART0 REQ2 INT_SPI1 REQ3 INT_RTC REQ4 INT_ADC REQ0 REQ1 REQ2 REQ3 REQ4 REQ5 R...

Page 360: ... In addition by changing the ARB_SEL bits we can rotate the priority of REQ1 to REQ4 Here if ARB_MODE bit is set to 0 ARB_SEL bits doesn t change automatically changed making the arbiter to operate in the fixed priority mode note that even in this mode we can reconfigure the priority by manually changing the ARB_SEL bits On the other hand if ARB_MODE bit is 1 ARB_SEL bits are changed in rotation f...

Page 361: ...gister In addition the SRCPND register is not affected by the priority logic of interrupt controller In the interrupt service routine for a specific interrupt source the corresponding bit of the SRCPND register has to be cleared to get the interrupt request from the same source correctly If you return from the ISR without clearing the bit the interrupt controller operates as if another interrupt r...

Page 362: ...Not requested 1 Requested 0 INT_DMA1 18 0 Not requested 1 Requested 0 INT_DMA0 17 0 Not requested 1 Requested 0 INT_LCD 16 0 Not requested 1 Requested 0 INT_UART2 15 0 Not requested 1 Requested 0 INT_TIMER4 14 0 Not requested 1 Requested 0 INT_TIMER3 13 0 Not requested 1 Requested 0 INT_TIMER2 12 0 Not requested 1 Requested 0 INT_TIMER1 11 0 Not requested 1 Requested 0 INT_TIMER0 10 0 Not requeste...

Page 363: ...ase note that only one interrupt source can be serviced in the FIQ mode in the interrupt controller you should use the FIQ mode only for the urgent interrupt Thus only one bit of INTMOD can be set to 1 Register Address R W Description Reset Value INTMOD 0X4A000004 R W Interrupt mode regiseter 0 IRQ mode 1 FIQ mode 0x00000000 Note If an interrupt mode is set to FIQ mode in the INTMOD register FIQ i...

Page 364: ...NT_SDI 21 0 IRQ 1 FIQ 0 INT_DMA3 20 0 IRQ 1 FIQ 0 INT_DMA2 19 0 IRQ 1 FIQ 0 INT_DMA1 18 0 IRQ 1 FIQ 0 INT_DMA0 17 0 IRQ 1 FIQ 0 INT_LCD 16 0 IRQ 1 FIQ 0 INT_UART2 15 0 IRQ 1 FIQ 0 INT_TIMER4 14 0 IRQ 1 FIQ 0 INT_TIMER3 13 0 IRQ 1 FIQ 0 INT_TIMER2 12 0 IRQ 1 FIQ 0 INT_TIMER1 11 0 IRQ 1 FIQ 0 INT_TIMER0 10 0 IRQ 1 FIQ 0 INT_WDT 9 0 IRQ 1 FIQ 0 INT_TICK 8 0 IRQ 1 FIQ 0 nBATT_FLT 7 0 IRQ 1 FIQ 0 INT_C...

Page 365: ...errupt request from the corresponding interrupt source note that even in such a case the corresponding bit of SRCPND register is set to 1 If the mask bit is 0 the interrupt request can be serviced Register Address R W Description Reset Value INTMSK 0X4A000008 R W Determine which interrupt source is masked The masked interrupt source will not be serviced 0 Interrupt service is available 1 Interrupt...

Page 366: ...ice available 1 Masked 1 INT_DMA1 18 0 Service available 1 Masked 1 INT_DMA0 17 0 Service available 1 Masked 1 INT_LCD 16 0 Service available 1 Masked 1 INT_UART2 15 0 Service available 1 Masked 1 INT_TIMER4 14 0 Service available 1 Masked 1 INT_TIMER3 13 0 Service available 1 Masked 1 INT_TIMER2 12 0 Service available 1 Masked 1 INT_TIMER1 11 0 Service available 1 Masked 1 INT_TIMER0 10 0 Service...

Page 367: ... 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 00 ARB_SEL1 10 9 Arbiter 1 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 00 ARB_SEL0 8 7 Arbiter 0 group priority order set 00 REQ 1 2 3 4 01 REQ 2 3 4 1 10 REQ 3 4 1 2 11 REQ 4 1 2 3 00 ARB_MODE6 6 Arbiter 6 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 ARB_MODE5 5 Ar...

Page 368: ...SRCPND register this register has to be cleared in the interrupt service routine after clearing the SRCPND register We can clear a specific bit of the INTPND register by writing a data to this register It clears only the bit positions of the INTPND register corresponding to those set to one in the data The bit positions corresponding to those that are set to 0 in the data remains as they are Regis...

Page 369: ...Not requested 1 Requested 0 INT_DMA1 18 0 Not requested 1 Requested 0 INT_DMA0 17 0 Not requested 1 Requested 0 INT_LCD 16 0 Not requested 1 Requested 0 INT_UART2 15 0 Not requested 1 Requested 0 INT_TIMER4 14 0 Not requested 1 Requested 0 INT_TIMER3 13 0 Not requested 1 Requested 0 INT_TIMER2 12 0 Not requested 1 Requested 0 INT_TIMER1 11 0 Not requested 1 Requested 0 INT_TIMER0 10 0 Not requeste...

Page 370: ...equest source 0x00000000 INT Source The OFFSET value INT Source The OFFSET value INT_ADC 31 INT_UART2 15 INT_RTC 30 INT_TIMER4 14 INT_SPI1 29 INT_TIMER3 13 INT_UART0 28 INT_TIMER2 12 INT_IIC 27 INT_TIMER1 11 INT_USBH 26 INT_TIMER0 10 INT_USBD 25 INT_WDT 9 INT_NFCON 24 INT_TICK 8 INT_UART1 23 nBATT_FLT 7 INT_SPI0 22 INT_CAM 6 INT_SDI 21 EINT8_23 5 INT_DMA3 20 EINT4_7 4 INT_DMA2 19 EINT3 3 INT_DMA1 ...

Page 371: ...it Description Initial State Reserved 31 13 Not used 0 INT_CAM_P 12 0 Not requested 1 Requested 0 INT_CAM_C 11 0 Not requested 1 Requested 0 INT_ADC_S 10 0 Not requested 1 Requested 0 INT_TC 9 0 Not requested 1 Requested 0 INT_ERR2 8 0 Not requested 1 Requested 0 INT_TXD2 7 0 Not requested 1 Requested 0 INT_RXD2 6 0 Not requested 1 Requested 0 INT_ERR1 5 0 Not requested 1 Requested 0 INT_TXD1 4 0 ...

Page 372: ... masked The masked interrupt source will not be serviced 0 Interrupt service is available 1 Interrupt service is masked 0xFFFF INTSUBMSK Bit Description Initial State Reserved 31 13 Not used 0 INT_CAM_P 12 0 Service available 1 Masked 1 INT_CAM_C 11 0 Service available 1 Masked 1 INT_ADC_S 10 0 Service available 1 Masked 1 INT_TC 9 0 Service available 1 Masked 1 INT_ERR2 8 0 Service available 1 Ma...

Page 373: ...port different requirements on the screen related to the number of horizontal and vertical pixels data line width for the data interface interface timing and refresh rate FEATURES STN LCD displays Supports 3 types of LCD panels 4 bit dual scan 4 bit single scan and 8 bit single scan display type Supports the monochrome 4 gray levels and 16 gray levels Supports 256 colors and 4096 colors for color ...

Page 374: ...D panel with touch panel and front light unit Reflective type LTS350Q1 PD2 TFT LCD panel only LTS350Q1 PE1 TFT LCD panel with touch panel and front light unit Transflective type LTS350Q1 PE2 TFT LCD panel only NOTE WinCE doesn t support the 12 bit packed data format Please check if WinCE can support the 12 bit color mode EXTERNAL INTERFACE SIGNAL STN TFT SEC TFT LTS350Q1 PD1 2 SEC TFT LTS350Q1 PE1...

Page 375: ...cial DMA the video data can be displayed on the screen without CPU intervention The VIDPRCS receives the video data from the LCDCDMA and sends the video data through the VD 23 0 data ports to the LCD driver after changing them into a suitable data format for example 4 8 bit single scan or 4 bit dual scan display mode The TIMEGEN consists of programmable logic to support the variable requirements o...

Page 376: ...VM Rate VLINE Rate 2 x MVAL The VFRAME and VLINE pulse generation relies on the configurations of the HOZVAL field and the LINEVAL field in the LCDCON2 3 registers Each field is related to the LCD size and display mode In other words the HOZVAL and LINEVAL can be determined by the size of the LCD panel and the display mode according to the following equation HOZVAL Horizontal display size Number o...

Page 377: ...e In other words users can select 4 gray levels among 16 gray levels by using the lookup table in the 4 gray level mode The gray levels cannot be selected in the 16 gray level mode all 16 gray levels must be chosen among the possible 16 gray levels In case of 256 color mode 3 bits are allocated for red 3 bits for green and 2 bits for blue The 256 colors mean that the colors are formed from the com...

Page 378: ...UT 11 8 REDLUT 7 4 and REDLUT 3 0 are assigned to each red level The possible combination of 4 bits each field is 16 and each red level should be assigned to one level among possible 16 cases In other words the user can select the suitable red level by using this type of lookup table For green color the GREENVAL 31 0 of the GREENLUT register is assigned as the lookup table as was done in the case ...

Page 379: ...at there are 6 times pixel on and one time pixel off The other cases for all gray levels are also shown in Table 15 2 In the STN LCD display we should be reminded of one item i e Flicker Noise due to the simultaneous pixel on and off on adjacent frames For example if all pixels on first frame are turned on and all pixels on next frame are turned off the Flicker Noise will be maximized To reduce th...

Page 380: ...onnected to the LCD driver and the 4 pins VD 7 4 for the LCD output are not used 8 bit Single Scan Display Type An 8 bit single scan display uses 8 parallel data lines to shift data to successive single horizontal lines of the display at a time until the entire frame has been shifted and transferred The 8 pins VD 7 0 for the LCD output from the LCD controller can be directly connected to the LCD d...

Page 381: ...r Memory Address Data 0000H A 31 0 0004H B 31 0 1000H L 31 0 1004H M 31 0 Mono 4 bit Single Scan Display 8 bit Single Scan Display Video Buffer Memory Address Data 0000H A 31 0 0004H B 31 0 0008H C 31 0 LCD Panel LCD Panel A 31 A 30 A 0 B 31 B 30 B 0 L 31 L 30 L 0 M 31 M 30 M 0 A 31 A 30 A 29 A 0 B 31 B 30 B 0 C 31 C 0 ...

Page 382: ... to 1 pixel The following table shows color data format in words Video data must reside at 3 word boundaries 8 pixel as follows RGB order DATA 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 Word 1 Red 1 Green 1 Blue 1 Red 2 Green 2 Blue 2 Red 3 Green 3 Word 2 Blue 3 Red 4 Green 4 Blue 4 Red 5 Green 5 Blue 5 Red 6 Word 3 Green 6 Blue 6 Red 7 Green 7 Blue 7 Red 8 Green 8 Blue 8 Unpacked 12 BPP Color mod...

Page 383: ...r will use only 12 bit color data It means that only upper 4bit each color data will be used as pixel data R 15 12 G 10 7 B 4 1 The following table shows color data format in words RGB order DATA 31 28 27 21 20 16 15 11 10 5 4 0 Word 1 Red 1 Green 1 Blue 1 Red 2 Green 2 Blue 2 Word 2 Red 3 Green 3 Blue 3 Red 4 Green 4 Blue 4 Word 3 Red 5 Green 5 Blue 5 Red 6 Green 6 Blue 6 ...

Page 384: ... 12 4 bit Dual Scan Display 4 bit Single Scan Display 8 bit Single Scan Display VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 Figure 15 2 Monochrome Display Types STN ...

Page 385: ...3 1 Pixel 4 bit Dual Scan Display VD3 R1 VD2 G1 VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 1 Pixel 4 bit Single Scan Display VD7 R1 VD6 G1 VD5 B1 VD4 R2 VD7 G2 VD6 B2 VD5 R3 VD4 G3 1 Pixel 8 bit Single Scan Display VD7 R1 VD6 G1 VD5 B1 VD4 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 Figure 15 3 Color Display Types STN ...

Page 386: ... s shift register the VLINE signal is asserted to display the line on the panel The VM signal provides an AC signal for the display The LCD uses the signal to alternate the polarity of the row and column voltages which are used to turn the pixels on and off because the LCD plasma tends to deteriorate whenever subjected to a DC voltage It can be configured to toggle on every frame or to toggle ever...

Page 387: ...ANK First Line Check Data Timing VFRAME VM VLINE VFRAME VM VLINE LINECNT VCLK VFRAME VM VLINE VCLK VD 7 0 WDLY WDLY Display the last line of the previous frame Full Frame Timing MMODE 1 MVAL 0x2 INT_FrSyn INT_FrSyn VFRAME VM VLINE Full Frame Timing MMODE 0 LINE1LINE2LINE3LINE4LINE5LINE6 LINE1 LINEn INT_FrSyn Figure 15 4 8 bit Single Scan Display Type STN LCD Timing ...

Page 388: ...l display size 1 LINEVAL Vertical display size 1 The rate of VCLK signal depends on the CLKVAL field in the LCDCON1 register Table 15 3 defines the relationship of VCLK and CLKVAL The minimum value of CLKVAL is 0 VCLK Hz HCLK CLKVAL 1 x2 The frame rate is VSYNC signal frequency The frame rate is related with the field of VSYNC VBPD VFPD LINEVAL HSYNC HBPD HFPD HOZVAL and CLKVAL in LCDCON1 and LCDC...

Page 389: ...P 0 BPP24BL 0 D 31 24 D 23 0 000H Dummy Bit P1 004H Dummy Bit P2 008H Dummy Bit P3 BSWP 0 HWSWP 0 BPP24BL 1 D 31 8 D 7 0 000H P1 Dummy Bit 004H P2 Dummy Bit 008H P3 Dummy Bit P1 P2 P3 P4 P5 LCD Panel VD Pin Descriptions at 24BPP VD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RED 7 6 5 4 3 2 1 0 GREEN 7 6 5 4 3 2 1 0 BLUE 7 6 5 4 3 2 1 0 ...

Page 390: ... 004H P4 P3 008H P6 P5 P1 P2 P3 P4 P5 LCD Panel VD Pin Descriptions at 16BPP 5 6 5 VD 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 RED 4 3 2 1 0 GREEN 5 4 3 2 1 0 BLUE NC NC 4 3 2 1 0 NC 5 5 5 I VD 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 RED 4 3 2 1 0 I GREEN 4 3 2 1 0 I BLUE NC NC 4 3 2 1 0 I NC NOTE ...

Page 391: ... be used as GPIO 8BPP Display BSWP 0 HWSWP 0 D 31 24 D 23 16 D 15 8 D 7 0 000H P1 P2 P3 P4 004H P5 P6 P7 P8 008H P9 P10 P11 P12 BSWP 1 HWSWP 0 D 31 24 D 23 16 D 15 8 D 7 0 000H P4 P3 P2 P1 004H P8 P7 P6 P5 008H P12 P11 P10 P9 P1 P2 P3 P4 P5 LCD Panel P6 P7 P8 P10 P11 P12 P9 ...

Page 392: ...23 20 D 19 16 D 15 12 D 11 8 D 7 4 D 3 0 000H P7 P8 P5 P6 P3 P4 P1 P2 004H P15 P16 P13 P14 P11 P12 P9 P10 008H P23 P24 P21 P22 P19 P20 P17 P18 2BPP Display BSWP 0 HWSWP 0 D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 000H P1 P2 P3 P4 P5 P6 P7 P8 004H P17 P18 P19 P20 P21 P22 P23 P24 008H P33 P34 P35 P36 P37 P38 P39 P40 D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000H P9 P10 P11 P12 P13 P14 P15 P16 ...

Page 393: ...R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 0X4D000404 FFH R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 0X4D0007FC Number of VD 23 22 21 20 19 15 14 13 12 11 10 7 6 5 4 3 Table 15 5 5 5 5 1 Format INDEX Bit Pos 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address 00H R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 I 0X4D000400 01H R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 I 0X4D000404 FFH R4 R3 R2 R1 R0 G4...

Page 394: ... A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 R4 B3 B2 B1 B0 I 1 2 3 4 5 LCD Panel 16BPP 5 6 5 Format Non Palette A 31 A 30 A 29 A 28 A 27 A 26 A 25 A 24 A 23 A 22 A 21 A 20 A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B...

Page 395: ...42B RISC MICROPROCESSOR LCD CONTROLLER 15 23 INT_FrSyn VSYNC HSYNC VDEN HSYNC VCLK VD LEND VBPD 1 VSPW 1 VFPD 1 HBPD 1 HFPD 1 HSPW 1 VDEN 1 Frame 1 Line LINEVAL 1 HOZVAL 1 Figure 15 6 TFT LCD Timing Example ...

Page 396: ...gital Data Inversion LCD_HCLK Horizontal Sampling Clock CPV Vertical Shift Clock STV Vertical Start Pulse LCCINV Source drive IC sampling inversion signal REV VCOM modulation Signal REVB Inversion Signal So LTS350Q1 PD1 2 and PE1 2 can be connected with the SC32442B without using the additional timing control logic But the user should additionally apply Vcom generator circuit various voltages INV ...

Page 397: ...ne 9 of virtual screen This is the data of line 10 of virtual screen This is the data of line 10 of virtual screen This is the data of line 11 of virtual screen This is the data of line 11 of virtual screen Before Scrolling View Port The same size of LCD panel LINEVAL 1 OFFSIZE PAGEWIDTH This is the data of line 1 of virtual screen This is the data of line 1 of virtual screen This is the data of l...

Page 398: ... on off control pin of the LCD panel the power of LCD panel is controlled by the setting of ENVID automatically The SC32442B also supports INVPWREN bit to invert polarity of the PWREN signal This function is available only when LCD panel has its own power on off control port and when port is connected to LCD_PWREN pin VSYNC HSYNC VDEN LCD_PWREN 1 FRAME ENVID LCD Panel On TFT LCD VLINE VFRAME STN L...

Page 399: ... 6 5 Select the display mode 00 4 bit dual scan display mode STN 01 4 bit single scan display mode STN 10 8 bit single scan display mode STN 11 TFT LCD panel 00 BPPMODE 4 1 Select the BPP Bits Per Pixel mode 0000 1 bpp for STN Monochrome mode 0001 2 bpp for STN 4 level gray mode 0010 4 bpp for STN 16 level gray mode 0011 8 bpp for STN color mode 256 color 0100 packed 12 bpp for STN color mode 4096...

Page 400: ...chronization period STN These bits should be set to zero on STN LCD 0x00 LINEVAL 23 14 TFT STN These bits determine the vertical size of LCD panel 0000000000 VFPD 13 6 TFT Vertical front porch is the number of inactive lines at the end of a frame before vertical synchronization period STN These bits should be set to zero on STN LCD 00000000 VSPW 5 0 TFT Vertical sync pulse width determines the VSY...

Page 401: ...mono mode x 120 cannot be supported because 1 line consists of 15 bytes Instead x 128 in mono mode can be supported because 1 line is composed of 16 bytes 2n LCD panel driver will discard the additional 8 dot 00000000000 HFPD TFT 7 0 TFT Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC 0X00 LINEBLANK STN STN These bits indicate the bl...

Page 402: ...MVAL 15 8 STN These bit define the rate at which the VM signal will toggle if the MMODE bit is set to logic 1 0X00 HSPW TFT 7 0 TFT Horizontal sync pulse width determines the HSYNC pulse s high level width by counting the number of the VCLK 0X00 WLH STN STN WLH 1 0 bits determine the VLINE pulse s high level width by counting the number of the HCLK WLH 7 2 are reserved 00 16 HCLK 01 32 HCLK 10 48 ...

Page 403: ... Porch 00 BPP24BL 12 TFT This bit determines the order of 24 bpp video memory 0 LSB valid 1 MSB Valid 0 FRM565 11 TFT This bit selects the format of 16 bpp output video data 0 5 5 5 1 Format 1 5 6 5 Format 0 INVVCLK 10 STN TFT This bit controls the polarity of the VCLK active edge 0 The video data is fetched at VCLK falling edge 1 The video data is fetched at VCLK rising edge 0 INVVLINE 9 STN TFT ...

Page 404: ...ignal polarity 0 normal 1 inverted 0 INVLEND 4 TFT This bit indicates the LEND signal polarity 0 normal 1 inverted 0 PWREN 3 STN TFT LCD_PWREN output signal enable disable 0 Disable PWREN signal 1 Enable PWREN signal 0 ENLEND 2 TFT LEND output signal enable disable 0 Disable LEND signal 1 Enable LEND signal 0 BSWP 1 STN TFT Byte swap control bit 0 Swap Disable 1 Swap Enable 0 HWSWP 0 STN TFT Half ...

Page 405: ...r Address R W Description Reset Value LCDSADDR2 0X4D000018 R W STN TFT Frame buffer start address 2 register 0x00000000 LCDSADDR2 Bit Description Initial State LCDBASEL 20 0 For dual scan LCD These bits indicate A 21 1 of the start address of the lower address counter which is used for the lower frame memory of dual scan LCD For single scan LCD These bits indicate A 21 1 of the end address of the ...

Page 406: ...ust be changed when ENVID bit is 0 Example 1 LCD panel 320 x 240 16gray single scan Frame start address 0x0c500000 Offset dot number 2048 dots 512 half words LINEVAL 240 1 0xef PAGEWIDTH 320 x 4 16 0x50 OFFSIZE 512 0x200 LCDBANK 0x0c500000 22 0x31 LCDBASEU 0x100000 1 0x80000 LCDBASEL 0x80000 0x50 0x200 x 0xef 1 0xa2b00 Example 2 LCD panel 320 x 240 16gray dual scan Frame start address 0x0c500000 O...

Page 407: ...table register 0x00000000 GREENLUT Bit Description Initial State GREENVAL 31 0 These bits define which of the 16 shades will be chosen by each of the 8 possible green combinations 000 GREENVAL 3 0 001 GREENVAL 7 4 010 GREENVAL 11 8 011 GREENVAL 15 12 100 GREENVAL 19 16 101 GREENVAL 23 20 110 GREENVAL 27 24 111 GREENVAL 31 28 0x00000000 BLUE Lookup Table Register Register Address R W Description Re...

Page 408: ...MODE 0X4D00004C R W STN Dithering mode register This register reset value is 0x00000 But user can change this value to 0x12210 Refer to a sample program source for the latest value of this register 0x00000 DITHMODE Bit Description Initial state DITHMODE 18 0 Use one of following value for your LCD 0x00000 or 0x12210 0x00000 ...

Page 409: ... 0X4D000050 R W TFT Temporary palette register This register value will be video data at next frame 0x00000000 TPAL Bit Description Initial state TPALEN 24 Temporary palette register enable bit 0 Disable 1 Enable 0 TPALVAL 23 0 Temporary palette value register TPALVAL 23 16 RED TPALVAL 15 8 GREEN TPALVAL 7 0 BLUE 0x000000 ...

Page 410: ...g bit 0 The interrupt has not been requested 1 LCD FIFO interrupt is requested when LCD FIFO reaches trigger level 0 LCD Source Pending Register Register Address R W Description Reset Value LCDSRCPND 0X4D000058 R W Indicate the LCD interrupt source pending register 0x0 LCDSRCPND Bit Description Initial state INT_FrSyn 1 LCD frame synchronized interrupt source pending bit 0 The interrupt has not be...

Page 411: ...The masked interrupt source will not be serviced 0x3 LCDINTMSK Bit Description Initial state FIWSEL 2 Determine the trigger level of LCD FIFO 0 4 words 1 8 words INT_FrSyn 1 Mask LCD frame synchronized interrupt 0 The interrupt service is available 1 The interrupt service is masked 1 INT_FiCnt 0 Mask LCD FIFO interrupt 0 The interrupt service is available 1 The interrupt service is masked 1 ...

Page 412: ..._SEL4 8 Select CPV signal pin 0 1 LCC_SEL3 7 Select CPV signal pin 1 1 LCC_SEL2 6 Select Line Dot inversion 0 LCC_SEL1 5 Select DG Normal mode 0 LCC_EN 4 Determine LCC3600 Enable Disable 0 LCC3600 Disable 1 LCC3600 Enable 0 CPV_SEL 3 Select CPV Pulse low width 0 MODE_SEL 2 Select DE Sync mode 0 Sync mode 1 DE mode 1 RES_SEL 1 Select output resolution type 0 320 x 240 1 240 x 320 0 LPC_EN 0 Determi...

Page 413: ...de dependent value Table 15 6 MV Value for Each Display Mode Mode MV Value Mono 4 bit single scan display 1 4 Mono 8 bit single scan display or 4 bit dual scan display 1 8 4 level gray 4 bit single scan display 1 4 4 level gray 8 bit single scan display or 4 bit dual scan display 1 8 16 level gray 4 bit single scan display 1 4 16 level gray 8 bit single scan display or 4 bit dual scan display 1 8 ...

Page 414: ...9 LINEBLANK 10 LCDBASEL LCDBASEU 3200 Note The higher the system load is the lower the CPU performance Example 2 Virtual screen register 4 level gray Virtual screen size 1024 x 1024 LCD size 320 x 240 LCDBASEU 0x64 4 bit dual scan 1 halfword 8 pixels 4 level gray Virtual screen 1 line 128 halfword 1024 pixels LCD 1 line 320 pixels 40 halfword OFFSIZE 128 40 88 0x58 PAGEWIDTH 40 0x28 LCDBASEL LCDBA...

Page 415: ...Guide The SC32442B LCD controller can support various LCD display sizes To select a suitable size for the flicker free LCD system application the user have to consider the LCD refresh bus bandwidth determined by the LCD display size bit per pixel bpp frame rate memory bus width memory type and so on LCD Data Rate Byte s bpp x Horizontal display size x Vertical display size x Frame rate 8 LCD DMA B...

Page 416: ...ns the system timing must be considered to avoid under run condition of the fifo of the lcd controller caused by memory bandwidth contention Example 4 TFT Resolution 240 x 240 VSPW 2 VBPD 14 LINEVAL 239 VFPD 4 HSPW 25 HBPD 15 HOZVAL 239 HFPD 1 CLKVAL 5 HCLK 60 M hz The parameters below must be referenced by LCD size and driver specifications VSPW VBPD LINEVAL VFPD HSPW HBPD HOZVAL and HFPD If targ...

Page 417: ...SC32442B RISC MICROPROCESSOR LCD CONTROLLER 15 45 NOTES ...

Page 418: ...own mode is supported Touch Screen Interface can control select pads XP XM YP YM of the Touch Screen for X Y position conversion Touch Screen Interface contains Touch Screen Pads control logic and ADC interface logic with an interrupt generation logic FEATURES Resolution 10 bit Differential Linearity Error 1 0 LSB Integral Linearity Error 2 0 LSB Maximum Conversion Rate 500 KSPS Low Power Consumpt...

Page 419: ...iting for Interrupt Mode INT_TC INT_ADC 8 1 MUX A D Converter ADC input control Touch Screen Pads control Interrupt Generation ADC interface Touch Screen Control AVDD AGND XP XM YP YM A 3 0 note note Figure 16 1 ADC and Touch Screen Interface Functional Block Diagram note symbol When Touch Screen device is used XM or PM is only connected ground for Touch Screen I F When Touch Screen device is not ...

Page 420: ...Interface generates the Interrupt source to Interrupt Controller Y Position Mode writes Y Position Conversion Data to ADCDAT1 so Touch Screen Interface generates the Interrupt source to Interrupt Controller 3 Auto Sequential X Y Position Conversion Mode Auto Sequential X Y Position Conversion Mode is operated as the following Touch Screen Controller sequentially converts X Position and Y Position ...

Page 421: ...return time of interrupt service routine and data access time With polling method by checking the ADCCON 15 end of conversion flag bit the read time from ADCDAT register can be determined 2 Another way for starting A D conversion is provided After ADCCON 1 A D conversion start by read mode is set to 1 A D conversion starts simultaneously whenever converted data is read XP X Tal CLK is used X Conve...

Page 422: ...5 NOTE ADC Freqeuncy should be set less than PCLK by 5times Ex PCLK 10MHZ ADC Freq 2MHz 0xFF SEL_MUX 5 3 Analog input channel select 000 AIN 0 001 AIN 1 010 AIN 2 011 AIN 3 100 YM 101 YP 110 XM 111 XP 0 STDBM 2 Standby mode select 0 Normal operation mode 1 Standby mode 1 READ_ START 1 A D conversion start by read 0 Disable start by read operation 1 Enable start by read operation 0 ENABLE_START 0 A...

Page 423: ... Switch Enable 0 XP Pull up Enable 1 XP Pull up Disable 1 AUTO_PST 2 Automatically sequencing conversion of X Position and Y Position 0 Normal ADC conversion 1 Auto Sequential measurement of X position Y position 0 XY_PST 1 0 Manually measurement of X Position or Y Position 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode 0 NOTE 1 While waiting...

Page 424: ...Description Initial State DELAY 15 0 1 Normal Conversion Mode XY Position Mode Auto Position Mode ADC conversion start delay value 2 Waiting for Interrupt Mode When Stylus Down occurs at SLEEP MODE generates Wake Up signal having interval several ms for Exiting SLEEP MODE Note Don t use Zero value 0x0000 00ff NOTE Before ADC conversion Touch screen uses X tal clock 3 68MHz During ADC conversion GC...

Page 425: ...pt Mode 0 Stylus down state 1 Stylus up state AUTO_PST 14 Automatic sequencing conversion of X Position and Y Position 0 Normal ADC conversion 1 Sequencing measurement of X position Y position XY_PST 13 12 Manually measurement of X Position or Y Position 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode Reserved 11 10 Reserved XPDATA Normal ADC ...

Page 426: ...rement of X position Y position XY_PST 13 12 Manually measurement of X Position or Y Position 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode Reserved 11 10 Reserved YPDATA 9 0 Y Position Conversion data value Data value 0 3FF ADC TOUCH SCREEN UP DOWN INT CHECK REGISTER ADCUPDN Register Address R W Description Reset Value ADCUPDN 0x5800014 R W...

Page 427: ...ADC AND TOUCH SCREEN INTERFACE SC32442B RISC MICROPROCESSOR 16 10 NOTES ...

Page 428: ...e time by second minute hour date day month and year The RTC unit works with an external 32 768 KHz crystal and also can perform the alarm function FEATURES BCD number second minute hour date day month and year Leap year generator Alarm function alarm interrupt or wake up from power off mode Year 2000 problem is removed Independent power pin RTCVDD Supports millisecond tick time interrupt for RTOS...

Page 429: ...he RTCCON register must be set high in order to write the BCD register in RTC block To display the second minute hour date month and year the CPU should read the data in BCDSEC BCDMIN BCDHOUR BCDDAY BCDDATE BCDMON and BCDYEAR registers respectively in the RTC block However a one second deviation may exist because multiple registers are read For example when the user reads the registers from BCDYEA...

Page 430: ...he count value reaches 0 when the tick time interrupt occurs Then the period of interrupt is as follows TICCNT fixed Period n 128 second n Tick time count value 1 127 TICCNT2 selectable by TICCNT2CLK n Tick time count value 1 65535 TICKCNT2CLK TICKCNT2 Frequency TICK Clock range s Resolution ms 3 b000 32768 2 15 0 2 0 03 3 b001 16384 2 14 0 4 0 06 3 b010 8192 2 13 0 8 0 12 3 b011 4096 2 12 0 16 0 ...

Page 431: ...al State CLKRST 3 RTC clock count reset 0 No reset 1 Reset 0 CNTSEL 2 BCD count select 0 Merge BCD counters 1 Reserved Separate BCD counters 0 CLKSEL 1 BCD clock select 0 XTAL 1 215 divided clock 1 Reserved XTAL clock only for test 0 RTCEN 0 RTC control enable 0 Disable 1 Enable Note Only BCD time count and read operation can be performed 0 Notes 1 All RTC registers have to be accessed for each by...

Page 432: ... mode Register Address R W Description Reset Value RTCALM 0x57000050 L 0x57000053 B R W by byte RTC alarm control register 0x0 RTCALM Bit Description Initial State Reserved 7 0 ALMEN 6 Alarm global enable 0 Disable 1 Enable 0 YEAREN 5 Year alarm enable 0 Disable 1 Enable 0 MONREN 4 Month alarm enable 0 Disable 1 Enable 0 DATEEN 3 Date alarm enable 0 Disable 1 Enable 0 HOUREN 2 Hour alarm enable 0 ...

Page 433: ... MIN DATA ALMMIN REGISTER Register Address R W Description Reset Value ALMMIN 0x57000058 L 0x5700005B B R W by byte Alarm minute data register 0x00 ALMMIN Bit Description Initial State Reserved 7 0 MINDATA 6 4 BCD value for alarm minute 0 5 000 3 0 0 9 0000 ALARM HOUR DATA ALMHOUR REGISTER Register Address R W Description Reset Value ALMHOUR 0x5700005C L 0x5700005F B R W by byte Alarm hour data re...

Page 434: ... 31 0 3 00 3 0 0 9 0001 ALARM MON DATA ALMMON REGISTER Register Address R W Description Reset Value ALMMON 0x57000064 L 0x57000067 B R W by byte Alarm month data register 0x01 ALMMON Bit Description Initial State Reserved 7 5 00 MONDATA 4 BCD value for alarm month 0 1 0 3 0 0 9 0001 ALARM YEAR DATA ALMYEAR REGISTER Register Address R W Description Reset Value ALMYEAR 0x57000068 L 0x5700006B B R W ...

Page 435: ...0 0 9 BCD MINUTE BCDMIN REGISTER Register Address R W Description Reset Value BCDMIN 0x57000074 L 0x57000077 B R W by byte BCD minute register Undefined BCDMIN Bit Description Initial State MINDATA 6 4 BCD value for minute 0 5 3 0 0 9 BCD HOUR BCDHOUR REGISTER Register Address R W Description Reset Value BCDHOUR 0x57000078 L 0x5700007B B R W by byte BCD hour register Undefined BCDHOUR Bit Descript...

Page 436: ... BCD DAY BCDDAY REGISTER Register Address R W Description Reset Value BCDDAY 0x57000080 L 0x57000083 B R W by byte BCD a day of the week register Undefined BCDDAY Bit Description Initial State Reserved 7 3 DAYDATA 2 0 BCD value for a day of the week 1 7 BCD MONTH BCDMON REGISTER Register Address R W Description Reset Value BCDMON 0x57000084 L 0x57000087 B R W by byte BCD month register Undefined B...

Page 437: ...er source s voltage drops below 1 3V max This flag is set to 1 After the initial power on it is set to 1 If this flag is set to 1 enter recovery from the backup state This means during the backup the power was low and all data need to be initialized 1 LOWBAT 1 as result of initial supply of power 2 If LOWBAT bit is 1 clear the bit to 0 after checking the RTCLBAT register 3 When the power supply is...

Page 438: ...E COUNTER 2 CONTROL REGISTER Register Address R W Description Reset Value TICCNT2CON 0x57000094 L R W Tick counter 2 control register Undefined TICCNT2CON Bit Description Initial State TICCNT2EN 3 Tick time counter 2 interrupt enable 0 Disable 1 Enable 0 TICCNT2CLK 2 0 Tick time counter 2 clock selection 3 b000 1 32768s 3 b001 1 16384s 3 b010 1 8192s 3 b011 1 4096s 3 b100 1 2048s 0 Note 1 Enable T...

Page 439: ... Current tick count value Note if TICCNT 7 and TICCNT2CON 3 disabled TICCURCNT should be 0 If you want to read the current tick counter value read the TICCURCNT value and then disable the TICCNT 7 and TICCNT2CON 3 RTC TICK TIME COUNTER SELECTION REGISTER Register Address R W Description Reset Value TICCNTSEL 0x5700009C L R W Tick counter selection Undefined TICCNTSEL Bit Description Initial State ...

Page 440: ... disturbed by malfunctions such as noise and system errors It can be used as a normal 16 bit interval timer to request interrupt service The watchdog timer generates the reset signal for 128 PCLK cycles FEATURES Normal interval timer mode with interrupt request Internal reset signal is activated for 128 PCLK cycles when the timer count value reaches 0 time out ...

Page 441: ...ency division factor can be selected as 16 32 64 or 128 Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle t_watchdog 1 PCLK Prescaler value 1 Division_factor WTDAT WTCNT Once the watchdog timer is enabled the value of watchdog timer data WTDAT register cannot be automatically reloaded into the timer counter WTCNT In this reason an...

Page 442: ... timer Register Address R W Description Reset Value WTCON 0x53000000 R W Watchdog timer control register 0x8021 WTCON Bit Description Initial State Prescaler value 15 8 Prescaler value The valid range is from 0 to 255 28 1 0x80 Reserved 7 6 Reserved These two bits must be 00 in normal operation 00 Watchdog timer 5 Enable or disable bit of Watchdog timer 0 Disable 1 Enable 1 Clock select 4 3 Determ...

Page 443: ...ister 0x8000 WTDAT Bit Description Initial State Count reload value 15 0 Watchdog timer count value for reload 0x8000 WATCHDOG TIMER COUNT WTCNT REGISTER The WTCNT register contains the current count values for the watchdog timer during normal operation Note that the content of the WTDAT register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initia...

Page 444: ...ic Freq System Clock P 1 z Normal and DMA data transfer mode byte halfword word transfer z DMA burst4 access support only word transfer z 1bit 4bit wide bus mode block stream mode switch support BLOCK DIAGRAM CMD Reg 5byte Resp Reg 17byte CMD Control 8bit Shift Reg CRC7 Prescaler FIFO 64byte DAT Control 8bit Shift Reg CRC16 4 DMA INT APB I F 8 8 8 8 32 32 32 32 32 32 PADDR PSEL PCLK PWDATA 31 0 PR...

Page 445: ...on 3 Confirm the end of SDI CMD path operation when the specific flag of SDICmdSta is set 4 The flag is CmdSent if command type is no response 5 The flag is RspFin if command type is with response 6 Clear the flags of SDICmdSta by writing 1 to the corresponding bit DAT Path Programming 1 Write data timeout period to SDIDTimer 2 Write block size block length to SDIBSize normally 0x80 word 3 Determi...

Page 446: ...2clocks after the completion of a data packet B The completion of sending the end bit of the next withdata command 2 Multi Block PrdType 0 the time between A and B restart at C A 2clocks after the completion of a data packet B 2clocks after A C 2clocks after the end bit of the abort command response 3 Multi Block PrdType 1 the time between A and B restart at A A 2clocks after the completion of a d...

Page 447: ...ore 1 receive SDIO Interrupt 0 Read Wait Enable RWaitEn 2 Determines read wait request signal generate when sd host waits the next block in multiple block read mode This bit needs to delay the next block to be transmitted from the card for SDIO 0 disable no generate 1 Read wait enable use SDIO 0 Reserved 1 Clock Out Enable ENCLK 0 Determines whether SDCLK Out enable or not 0 disable prescaler off ...

Page 448: ... Value Reserved 31 13 Abort Command AbortCmd 12 Determines whether command type is for abort for SDIO 0 normal command 1 abort command CMD12 CMD52 0 Command with Data WithData 11 Determines whether command type is with data for SDIO 0 without data 1 with data 0 LongRsp 10 Determines whether host receives a 136 bit long response or not 0 short response 1 long response 0 WaitRsp 9 Determines whether...

Page 449: ...to one this bit 0 not detect 1 timeout 0 Response Receive End RspFin 9 R C Command response received This flag is cleared by setting to one this bit 0 not detect 1 response end 0 CMD line progress On CmdOn 8 Command transfer in progress 0 not detect 1 in progress 0 RspIndex 7 0 Response index 6bit with start 2bit 8bit 0x00 SDI Response Register 0 SDIRSP0 Register Address R W Description Reset Valu...

Page 450: ... Response3 31 0 unused short card status 31 0 long 0x00000000 SDI Data Busy Timer Register SDIDTimer Register Address R W Description Reset Value SDIDTimer 0x5A000024 R W SDI Data Busy Timer Register 0x0 SDIDTimer Bit Description Initial Value Reserved 31 23 DataTimer 22 0 Data Busy timeout period 0x10000 SDI Block Size Register SDIBSize Register Address R W Description Reset Value SDIBSize 0x5A00...

Page 451: ...MD 19 Determines when data receive start after command sent or not 0 directly after DatMode set 1 after command sent assume DatMode sets to 2 b10 0 Busy After Command BACMD 18 Determines when busy receive start after command sent or not 0 directly after DatMode set 1 after command sent assume DatMode sets to 2 b01 0 Block mode BlkMode 17 Data transfer mode 0 stream data transfer 1 block data trans...

Page 452: ...it request occur 0 SDIO Interrupt Detect IOIntDet 9 R C SDIO interrupt detect This flag is cleared by setting to one this bit 0 not detect 1 SDIO interrupt detect 0 Reserved 8 CRC Status Fail CrcSta 7 R C CRC Status error when data block sent CRC check failed This flag is cleared by setting to one this bit 0 not detect 1 crc status fail 0 Data Receive CRC Fail DatCrc 6 R C Data block received erro...

Page 453: ...This bit indicates that FIFO data is available for receive when DatMode is data receive mode If DMA mode is enable sd host requests DMA operation 0 not detect FIFO empty 1 detect 1 FIFO 64 0 Tx FIFO Half Full TFHalf 11 This bit sets to 1 whenever Tx FIFO is less than 33byte 0 33 Tx FIFO 64 1 0 Tx FIFO 32 0 Tx FIFO Empty TFEmpty 10 This bit sets to 1 whenever Tx FIFO is empty 0 1 Tx FIFO 64 1 Empty...

Page 454: ...le 1 interrupt enable 0 FFfail Interrupt Enable FFfailInt 11 Determines SDI generate an interrupt if FIFO fail error occurs 0 disable 1 interrupt enable 0 CrcSta Interrupt Enable CrcStaInt 10 Determines SDI generate an interrupt if CRC status error occurs 0 disable 1 interrupt enable 0 DatCrc Interrupt Enable DatCrcInt 9 Determines SDI generate an interrupt if data receive CRC failed 0 disable 1 i...

Page 455: ...00041 Bi HW 0x5A000043 Bi B R W SDI Data Register 0x0 SDIDAT Bit Description Initial State Data Register 31 0 This field contains the data to be transmitted or received over the SDI channel 0x00000000 Li W Li HW Li B Access by Word HalfWord Byte unit when endian mode is Little Bi W Access by Word unit when endian mode is Big Bi HW Access by HalfWord unit when endian mode is Big Bi B Access by Byte...

Page 456: ...master IIC bus control status register IICSTAT Multi master IIC bus Tx Rx data shift register IICDS Multi master IIC bus address register IICADD When the IIC bus is free the SDA and SCL lines should be both at High level A High to Low transition of SDA can initiate a Start condition A Low to High transition of SDA can initiate a Stop condition while SCL remains steady at High Level The Start and S...

Page 457: ...ERFACE SC32442B RISC MICROPROCESSOR 20 2 PCLK Address Register SDA 4 bit Prescaler IIC Bus Control Logic IICSTAT IICCON Comparator Shift Register Shift Register IICDS Data Bus SCL Figure 20 1 IIC Bus Block Diagram ...

Page 458: ...p condition can terminate the data transfer A Stop condition is a Low to High transition of the SDA line while SCL is High Start and Stop conditions are always generated by the master The IIC bus gets busy when a Start condition is generated A Stop condition will make the IIC bus free When a master initiates a Start condition it should send a slave address to notify the slave device One byte of ad...

Page 459: ... 3 IIC Bus Interface Data Format SDA Acknowledgement Signal from Receiver SCL S 1 2 7 8 9 1 2 9 Acknowledgement Signal from Receiver MSB ACK Byte Complete Interrupt within Receiver Clock Line Held Low by receiver and or transmitter Figure 20 4 Data Transfer on the IIC Bus ACK SIGNAL TRANSMISSION To complete a one byte transfer operation the receiver should send an ACK bit to the transmitter The AC...

Page 460: ... ninth SCL pulse The ACK bit transmit function can be enabled or disabled by software IICSTAT However the ACK pulse on the ninth clock of SCL is required to complete the one byte data transfer operation Data Output by Transmitter Data Output by Receiver SCL from Master Start Condition Clock Pulse for Acknowledgment Clock to Output 9 8 7 S 1 2 Figure 20 5 Acknowledge on the IIC Bus ...

Page 461: ...not For the purpose of evaluation is that each master should detect the address bits While each master generates the slaver address it should also detect the address bit on the SDA line because the SDA line is likely to get Low rather than to keep High Assume that one master generates a Low as first address bit while the other master is maintaining High In this case both masters will detect Low on...

Page 462: ...3 Set IICSTAT to enable Serial Output Write slave address to IICDS Write 0xF0 M T Start to IICSTAT The data of the IICDS is transmitted ACK period and then interrupt is pending Write 0xD0 M T Stop to IICSTAT Write new data transmitted to IICDS Stop Clear pending bit to resume The data of the IICDS is shifted to SDA START Master Tx mode has been configured Clear pending bit Wait until the stop cond...

Page 463: ...ve address is transmitted ACK period and then interrupt is pending Write 0x90 M R Stop to IICSTAT Read a new data from IICDS Stop Clear pending bit to resume SDA is shifted to IICDS START Master Rx mode has been configured Clear pending bit Wait until the stop condition takes effect END Y N Figure 20 7 Operations for Master Receiver Mode ...

Page 464: ...s IICADD and IICDS the received slave address Write data to IICDS The IIC address match interrupt is generated Clear pending bit to resume The data of the IICDS is shifted to SDA START Slave Tx mode has been configured END Matched N Y Stop Interrupt is pending N Y Figure 20 8 Operations for Slave Transmitter Mode ...

Page 465: ...C compares IICADD and IICDS the received slave address Read data from IICDS The IIC address match interrupt is generated Clear pending bit to resume SDA is shifted to IICDS START Slave Rx mode has been configured END Matched N Y Stop Interrupt is pending N Y Figure 20 9 Operations for Slave Receiver Mode ...

Page 466: ...errupt pending when read 2 Clear pending condition Resume the operation when write 1 1 Interrupt is pending when read 2 N A when write 0 Transmit clock value 4 3 0 IIC Bus transmit clock prescaler IIC Bus transmit clock frequency is determined by this 4 bit prescaler value according to the following formula Tx clock IICCLK IICCON 3 0 1 Undefined Notes 1 Interfacing with EEPROM the ack generation m...

Page 467: ...S will be transferred automatically just after the start signal 0 Serial output 4 IIC bus data output enable disable bit 0 Disable Rx Tx 1 Enable Rx Tx 0 Arbitration status flag 3 IIC bus arbitration procedure status flag bit 0 Bus arbitration successful 1 Bus arbitration failed during serial I O 0 Address as slave status flag 2 IIC bus address as slave status flag bit 0 Cleared when START STOP co...

Page 468: ...e read any time regardless of the current serial output enable bit IICSTAT setting Slave address 7 1 Not mapped 0 XXXXXXXX MULTI MASTER IIC BUS TRANSMIT RECEIVE DATA SHIFT IICDS REGISTER Register Address R W Description Reset Value IICDS 0x5400000C R W IIC Bus transmit receive data shift register 0xXX IICDS Bit Description Initial State Data shift 7 0 8 bit data shift register for IIC bus Tx Rx op...

Page 469: ...LC Bit Description Initial State Filter Enable 2 IIC bus filter enable bit When SDA port is operating as input this bit should be High This filter can prevent from occurred error by a glitch during double of PCLK time 0 Filter disable 1 Filter enable 0 SDA output delay 1 0 IIC Bus SDA line delay length selection bits SDA line is delayed as following clock time PCLK 00 0 clocks 01 5 clocks 10 10 cl...

Page 470: ...ound The SC32442B Inter IC Sound IIS bus interface can be used to implement a CODEC interface to an external 8 16 bit stereo audio CODEC IC for mini disc and portable applications The IIS bus interface supports both IIS bus data format and MSB justified data format The interface provides DMA transfer mode for FIFO access instead of an interrupt It can transmit and receive data simultaneously as we...

Page 471: ...e master clock Channel generator and state machine CHNC IISCLK and IISLRCK are generated and controlled by the channel state machine 16 bit shift register SFTR Parallel data is shifted to serial data output in the transmit mode and serial data input is shifted to parallel data in the receive mode TRANSMIT OR RECEIVE ONLY MODE Normal transfer IIS control register has FIFO ready flag bits for transm...

Page 472: ...the missing bits are set to zero internally And therefore the MSB has a fixed position whereas the position of the LSB depends on the word length The transmitter sends the MSB of the next word at one clock period whenever the IISLRCK is changed Serial data sent by the transmitter may be synchronized with either the trailing HIGH to LOW or the leading LOW to HIGH edge of the clock signal However th...

Page 473: ...ade by IIS prescaler the prescaler value and Master clock type 256 or 384fs should be determined properly Serial bit clock frequency type 16 32 48fs can be selected by the serial bit per channel and Master clock as shown in Table 21 2 Table 21 1 CODEC clock CODECLK 256 or 384fs IISLRCK fs 8 000 KHz 11 025 KHz 16 000 KHz 22 050 KHz 32 000 KHz 44 100 KHz 48 000 KHz 64 000 KHz 88 200 KHz 96 000 KHz 2...

Page 474: ...d only 6 0 Full 1 Not full 0 Transmit DMA service request 5 0 Disable 1 Enable 0 Receive DMA service request 4 0 Disable 1 Enable 0 Transmit channel idle command 3 In Idle state the IISLRCK is inactive Pause Tx 0 Not idle 1 Idle 0 Receive channel idle command 2 In Idle state the IISLRCK is inactive Pause Rx 0 Not idle 1 Idle 0 IIS prescaler 1 0 Disable 1 Enable 0 IIS interface 0 0 Disable stop 1 E...

Page 475: ...ve mode 10 Transmit mode 11 Transmit and receive mode 00 Active level of left right channel 5 0 Low for left channel High for right channel 1 High for left channel Low for right channel 0 Serial interface format 4 0 IIS compatible format 1 MSB Left justified format 0 Serial data bit per channel 3 0 8 bit 1 16 bit 0 Master clock frequency select 2 0 256fs 1 384fs fs sampling frequency 0 Serial bit ...

Page 476: ...Prescaler A makes the master clock that is used the internal block and division factor is N 1 00000 Prescaler control B 4 0 Data value 0 31 Note Prescaler B makes the master clock that is used the external block and division factor is N 1 00000 Notes 1 The IISPSR register is accessible for each byte halfword and word unit using STRB STRH STR and LDRB LDRH LDR instructions or char short int int typ...

Page 477: ...DRH LDR instructions or short int int type pointer in Little Big endian mode 2 Li HW W Little HalfWord Word Bi HW W Big HalfWord Word IIS FIFO IISFIFO REGISTER IIS bus interface contains two 64 byte FIFO for the transmit and receive mode Each FIFO has 16 width and 32 depth form which allows the FIFO to handles data for each halfword unit regardless of valid data size Transmit and receive FIFO acce...

Page 478: ...y 8 bit serial data at a frequency is determined by its corresponding control register settings If you only want to transmit receive data can be kept dummy Otherwise if you only want to receive you should transmit dummy 1 data There are 4 I O pin signals associated with SPI transfers SCK SPICLK0 1 MISO SPIMISO0 1 data line MOSI SPIMOSI0 1 data line and active low SS nSS0 1 pin input FEATURES Suppo...

Page 479: ... DCOL REDY APB I F 0 INT DMA 0 Master Slave Slave Master Slave Slave Master Data Bus INT 0 INT 1 REQ0 REQ1 ACK0 ACK1 SS nSS 1 SCK SPICLK 1 MOSI SPIMOSI 1 MISO SPIMISO 1 Pin Control Logic 1 MSTR Tx 8bit Shift Reg 1 Rx 8bit Shift Reg 1 LSB MSB LSB MSB 8 8 Clock SPI Clock Master CPOL CPHA CLOCK Logic 1 MULF DCOL REDY APB I F 1 INT DMA 1 Master Slave Slave Master Slave Slave Master INT 0 INT 1 REQ0 RE...

Page 480: ...ivated before writing byte data to SPTDATn PROGRAMMING PROCEDURE When a byte data is written into the SPTDATn register SPI starts to transmit if ENSCK and MSTR of SPCONn register are set You can use a typical programming procedure to operate an SPI card To program the SPI modules follow these basic steps 1 Set Baud Rate Prescaler Register SPPREn 2 Set SPCONn to configure properly the SPI module 3 ...

Page 481: ... Format B Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB SPICLK MISO MSB CPOL 1 CPHA 0 Format A Cycle MOSI 1 2 3 4 5 6 7 8 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB SPICLK MISO LSB CPOL 0 CPHA 1 Format B Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB SPICLK MISO MSB CPOL 0 CPHA 0 Format A LSB MSB MSB MSB MSB of previous frame LSB LSB of next frame LSB LSB of next fram...

Page 482: ...es for dummy byte pull out 3 SPI is configured as DMA start with SMOD bits 4 DMA is configured properly 5 SPI receives 1byte data from card 6 SPI requests DMA service 7 DMA receives the data from the SPI 8 Write data 0xFF automatically to SPTDATn 9 Return to Step 6 until DMA count becomes 0 10 SPI is configured as polling mode with SMOD bits 11 If SPSTAn s READY flag is set then read the last byte...

Page 483: ...er you want SCK enabled or not master only 0 disable 1 enable 0 Master Slave Select MSTR 3 Determine the desired mode master or slave 0 slave 1 master Note In slave mode there should be set up time for master to initiate Tx Rx 0 Clock Polarity Select CPOL 2 Determine an active high or active low clock 0 active high 1 active low 0 Clock Phase Select CPHA 1 Select one of the two fundamentally differ...

Page 484: ... REGISTER When the SPI system is enabled the direction of pins except nSS pin is controlled by MSTR bit of SPCONn register The direction of nSS pin is always input When the SPI is a master nSS pin is used to check multi master error provided that the SPPIN s ENMUL bit is active and another GPIO should be used to select a slave If the SPI is configured as a slave the nSS pin is used to select SPI a...

Page 485: ...D RATE PRESCALER REGISTER Register Address R W Description Reset Value SPPRE0 0x5900000C R W SPI cannel 0 baud rate prescaler register 0x00 SPPRE1 0x5900002C R W SPI cannel 1 baud rate prescaler register 0x00 SPPREn Bit Description Initial State Prescaler Value 7 0 Determine SPI clock rate Baud rate PCLK 2 Prescaler value 1 0x00 NOTE Baud rate should be less than 25 MHz SPI TX DATA REGISTER Regist...

Page 486: ...ideo sync signals and pixel clock polarity can be inverted in the CAMIF side by using register setting FEATURES ITU R BT 601 656 8 bit mode external interface support DZI Digital Zoom In capability Programmable polarity of video sync signals Max 4096 x 4096 pixel input support without scaling 2048 x 2048 pixel input support with scaling Max 4096 x 4096 pixel output support for CODEC path Max 640 x...

Page 487: ...OPROCESSOR CAMERA INTERFACE 23 2 BLOCK DIAGRAM YCbCr 4 2 2 T_patternMux CatchCam YCbCr 4 2 X Preview Scaler RGB Formatter Codec Scaler Preview DMA ITU R BT 601 656 Codec DMA CamI f SFR AHB bus Figure 23 1 CAMIF Overview ...

Page 488: ...ng Diagram CAMPCLK CAMDATA 7 0 Cr FF 00 00 XY Cb Y FF 00 00 XY Video timing reference codes Pixel data Video timing reference codes Figure 23 3 ITU R BT 656 Input Timing Diagram There are two timing reference signals in ITU R BT 656 format one is at the beginning of each video data block start of active video SAV and other is at the end of each video data block end of active video EAV as shown in ...

Page 489: ...0 0 For compatibility with existing 8 bit interfaces the values of bits D1 and D0 are not defined F 0 during field 1 1 during field 2 V 0 elsewhere 1 during field blanking H 0 in SAV Start of Active Video 1 in EAV End of Active Video P0 P1 P2 P3 protection bit Camera interface logic can catch the video sync bits like H SAV EAV and V Frame Sync after reserved data as FF 00 00 NOTE All external came...

Page 490: ...2 CAMIF External Camera Processor Frame Memory SDRAM P port C port ITU format PIP RGB Codec image YCbCr 4 2 0 or YCbCr 4 2 2 Window cut Figure 23 4 Two DMA Paths CLOCK DOMAIN CAMIF has two clock domains One is the system bus clock which is HCLK The other is the pixel clock which is CAMPCLK The system clock must be faster than pixel clock Figure 23 5 shows CAMCLKOUT must be divided from the fixed f...

Page 491: ...LK Normally use Schmit triggere d Level shifter Figure 23 5 CAMIF Clock Generation C port Y 1 C port Cb 1 C port Cr 1 C port Y 2 C port Cb 2 C port Cr 2 C port Y 3 C port Cb 3 C port Cr 3 C port Y 4 C port Cb 4 C port Cr 4 P port RGB 1 P port RGB 2 P port RGB 3 P port RGB 4 4 pingpong Frame memory SDRAM ITU 601 656 YCbCr 4 2 2 8 bits Camera Interface AHB bus Memorycontroller P port RGB 4 4 4 C por...

Page 492: ...o pixels are one word for RGB 16 bit format Please refer the following figure Camera Interface Y frame memory PCLK DATA ITU 601 656 YCbCr 4 2 2 8 bit input timing Cb frame memory Cr frame memory Little endian method time Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Y4 Y3 Y2 Y1 Y8 Y7 Y6 Y5 Cb4 Cb3 Cb2 Cb1 Cb8 Cb7 Cb6 Cb5 Little endian method Cr4 Cr3 Cr2 Cr1 Cr8 Cr7 Cr6 Cr5 Little endian method RGB frame memory 24 b...

Page 493: ...specially capture operation should be disabled when related information for target size are changed CAMVSYNC CAMHREF INTERRUPT SFR setting ImgCptEn Multi frame capturing Reserved Image Capture Frame Capture Start CAMVSYNC CAMHREF INTERRUPT New SFR command in ISR In Capturing Reserved Image Capture New command valid timing diagram New Command Figure 23 8 Timing Diagram for Register Setting NOTE FIF...

Page 494: ...t is recommended that ImgCptEn ImgCptEn_CoSc ImgCptEnPrSC are set at same time and at last of SFR setting in ISR FrameCnt which is read in ISR means next frame count On following diagram last captured frame count is 1 That is Frame 1 is the last captured frame among frame 0 3 FrameCnt is increased by 1 at IRQ rising ISR region ISR region ISR region VSYNC ISR region ImgCptEn cmd LastIRQEn Capture O...

Page 495: ...This bit is reserved and the value must be 0 0 SourceHsize 28 16 Source Horizontal Pixel Number must be multiple of 8 0 Order422 15 14 Input YcbCr order inform for input 8 bit mode 00 YCbYCr 01 YCrYCb 10 CbYCrY 11 CrYCbY 0 SourceVsize 12 0 Source Vertical Pixel Number 0 Note We recommend a following sequence for preventing FIFO overflow at first frame of capture operation in CODEC path ITU 601 For...

Page 496: ...e 640 PreHorRatio_Pr 2 0 ClrOvCoFiCb 15 0 Normal 1 Clear the overflow indication flag of input CODEC FIFO Cb 0 ClrOvCoFiCr 14 0 Normal 1 Clear the overflow indication flag of input CODEC FIFO Cr 0 ClrOvPrFiCb 13 0 Normal 1 Clear the overflow indication flag of input PREVIEW FIFO Cb 0 ClrOvPrFiCr 12 0 Normal 1 Clear the overflow indication flag of input PREVIEW FIFO Cr 0 WinVerOfst 10 0 Window Vert...

Page 497: ...orizontal increment test pattern 11 Vertical increment test pattern 0 InvPolCAMPCLK 26 0 Normal 1 Inverse the polarity of CAMPCLK 0 InvPolCAMVSYN C 25 0 Normal 1 Inverse the polarity of CAMVSYNC 0 InvPolCAMHREF 24 0 Normal 1 Inverse the polarity of CAMHREF 0 Y1 START ADDRESS REGISTER Register Address R W Description Reset Value CICOYSA1 0x4F000018 RW Y 1st frame start address for codec DMA 0 CICOY...

Page 498: ... 0 CB1 START ADDRESS REGISTER Register Address R W Description Reset Value CICOCBSA1 0x4F000028 RW Cb 1st frame start address for codec DMA 0 CICOCBSA1 Bit Description Initial State CICOCBSA1 31 0 Cb 1st frame start address for codec DMA 0 CB2 START ADDRESS REGISTER Register Address R W Description Reset Value CICOCBSA2 0x4F00002C RW Cb 2nd frame start address for codec DMA 0 CICOCBSA2 Bit Descrip...

Page 499: ...ec DMA 0 CR2 START ADDRESS REGISTER Register Address R W Description Reset Value CICOCRSA2 0x4F00003C RW Cr 2nd frame start address for codec DMA 0 CICOCRSA2 Bit Description Initial State CICOCRSA2 31 0 Cr 2nd frame start address for codec DMA 0 CR3 START ADDRESS REGISTER Register Address R W Description Reset Value CICOCRSC3 0x4F000040 RW Cr 3rd frame start address for codec DMA 0 CICOCRSC3 Bit D...

Page 500: ...input image format 0 Out422_Co 30 0 YCbCr 4 2 0 codec scaler output image format This mode is mainly for MPEG 4 codec H W JPEG DCT normally used 1 YCbCr 4 2 2 codec scaler output image format This mode is mainly for S W JPEG 0 TargetHsize_Co 28 16 Horizontal pixel number of target image for codec DMA multiple of 16 0 FlipMd_Co 15 14 Image mirror and rotation for codec DMA 00 Normal 01 X axis mirro...

Page 501: ...r codec Cb Cr frames 0 LastIRQEn_Co 2 0 normal 1 enable last IRQ at the end of the frame capture This bit is cleared automatically 0 NOTE All burst lengths must be one of the 2 4 8 16 Example 1 Target image size QCIF horizontal Y width 176 pixels 1 pixel 1 Byte 1 word 4 pixel 176 4 44 word 44 8 4 main burst 8 remained burst 4 Example 2 Target image size VGA horizontal Y width 640 pixels 1 pixel 1 ...

Page 502: ...e_Pr DST_Width TargetHsize_xx DST_Height TargetVsize_xx TargetHsize_xx TargetHsize_Co or TargetHsize_Pr DST_Width TargetHsize_xx DST_Height TargetVsize_xx SRC_Width SourceHsize 2 x WinHorOfst SRC_Height SourceVsize 2 x WinVerOfst Figure 23 12 Scaling Scheme The other control registers of pre scaled like image size pre scale ratio pre scale shift ratio and main scale ratio are defined according to ...

Page 503: ...2048 pixel line buffer So upper 1280 pixels input images must be pre scaled by over 1 2 for capturing valid preview image SourceHsize 2 WinHorOfst PreHorRatio_Pr 640 CODEC PRE SCALER CONTROL REGISTER 1 Register Address R W Description Reset Value CICOSCPRERATIO 0x4F000050 RW Codec pre scaler ratio control 0 CICOSCPRERATIO Bit Description Initial State SHfactor_Co 31 28 Shift factor for codec pre s...

Page 504: ...age for DSC application In this case input pixel buffering depends on only input FIFOs so the system bus should be not busy in this mode 0 ScaleUpDown_Co 30 29 Scale up down flag for codec scaler In 1 1 scale ratio this bit should be 1 00 down 11 up 00 MainHorRatio_Co 24 16 Horizontal scale ratio for codec main scaler 0 CoScalerStart 15 Codec scaler start 0 MainVerRatio_Co 8 0 Vertical scale ratio...

Page 505: ...unter value indicates the next frame number 0 WinOfstEn_Co 25 Window offset enable status 0 FlipMd_Co 24 23 Flip mode of codec DMA 0 ImgCptEn_CamIf 22 Image capture enable of camera interface 0 ImgCptEn_CoSC 21 Image capture enable of codec path 0 RGB1 START ADDRESS REGISTER Register Address R W Description Reset Value CIPRCLRSA1 0x4F00006C RW RGB 1st frame start address for preview DMA 0 CIPRCLRS...

Page 506: ...it Description Initial State CIPRCLRSA4 31 0 RGB 4th frame start address for preview DMA 0 PREVIEW TARGET FORMAT REGISTER Register Address R W Description Reset Value CIPRTRGFMT 0x4F00007C RW Target image format of preview DMA 0 CIPRTRGFMT Bit Description Initial State TargetHsize_Pr 28 16 Horizontal pixel number of target image for preview DMA even 0 FlipMd_Pr 15 14 Image mirror and rotation for ...

Page 507: ...the 2 4 8 16 Example 1 Target image size QCIF for RGB 32 bit format horizontal width 176 pixels 1 pixel 1 word 176 pixel 176 word 176 16 0 main burst 16 remained burst 16 Example 2 Target image size VGA for RGB 16 bit format horizontal width 640 pixels 2 pixel 1 word 640 2 320 word 160 16 0 main burst 16 remained burst 16 PREVIEW PRE SCALER CONTROL REGISTER 1 Register Address R W Description Reset...

Page 508: ... CICOSCCTRL Bit Description Initial State Sample_Pr 31 Sampling method for format conversion This bit is recommended to fix 1 0 RGBformat_Pr 30 0 16 bit RGB 1 24 bit RGB 0 ScaleUpDown_Pr 29 28 Scale up down flag for preview scaler In 1 1 scale ratio this bit should be 1 00 down 11 up 00 MainHorRatio_Pr 24 16 Horizontal scale ratio for preview main scaler 0 PrScalerStart 15 Preview scaler start 0 M...

Page 509: ... preview DMA 0 FlipMd_Pr 24 23 Flip mode of preview DMA 0 ImgCptEn_PrSC 21 Image capture enable of preview path 0 IMAGE CAPTURE ENABLE REGISTER This register must be set at last Register Address R W Description Reset Value CIIMGCPT 0x4F0000A0 RW Image capture enable command 0 CIGCTRL Bit Description Initial State ImgCptEn 31 Camera interface global capture enable 0 ImgCptEn_CoSc 30 Capture enable ...

Page 510: ...ntroller LCD_DMA CAMIF DMA DMA0 DMA1 DMA2 DMA3 USB_HOST_DMA EXT_BUS_MASTER Test interface controller TIC and ARM920T The following list shows the priorities among these bus masters after a reset 1 DRAM refresh controller 2 LCD_DMA 3 CAMIF codec DMA 4 CAMIF preview DMA 5 DMA0 6 DMA1 7 DMA2 8 DMA3 9 USB host DMA 10 External bus master 11 TIC 12 ARM920T 13 Reserved Among these bus masters the four DM...

Page 511: ...BUS PRIORITIES SC32442B RISC MICROPROCESSOR 24 2 NOTES ...

Page 512: ...V VDD 1 8 VDDOP 3 3V VDD 4 8 VDDOP1 3 3V VDD 4 8 VDDOP2 3 3V VDD 4 8 VDDOP3 2 8V VDD 4 8 VDDMOP 1 8V VDD 4 8 VDDRTC 1 8V 2 5V 3 0V 3 3V VDD 4 5 DC Supply Voltage VDDADC 3 3V VDD 4 8 3 3V Input buffer 6 5 DC Input Voltage VIN 3 3V Interface 5V Tolerant input buffer 4 8 DC Output Voltage VOUT 3 3V Output buffer V DC Input Latch up Current IIN 200 mA Storage Temperature TSTG 65 to 150 o C ...

Page 513: ...OP 4 1 7 1 8 1 95 DC Supply Voltage for Analog Core VDDadc 2 7 3 3 3 6 DC Supply Voltage for RTC VDDRTC 1 5 1 8 3 6 V Operating Temperature TOPR Extended 25 to 85 o C Note 1 50 66 100 125 133MHz mean the frequencies that arm and internal be able to operate when applying DVS scheme The right side values are DC spec at this condition 2 In the DVS VDDiarm VDDi VDDpll can be supplied with same voltage...

Page 514: ... 879 45 18 µA Low level input current Input buffer IIL Input buffer with pull up VIN VSS 10 17 32 85 µA High level output voltage IOH 10 uA 1 6995 IOH 100 uA 1 6950 Type B6 IOH 6 mA 1 159 1 559 1 889 Type B8 IOH 8 mA 1 159 1 559 1 886 Type B10 IOH 10 mA 1 159 1 559 1 886 VOH Type B12 IOH 12 mA 1 159 1 559 1 886 V Low level output voltage IOL 10 uA 0 475mV IOL 100 uA 4 744mV Type B6 IOL 6 mA 0 126 ...

Page 515: ...rent Input buffer 10 10 IIH Input buffer with pull down VIN VDD 10 33 60 µA Low level input current IIL Input buffer VIN VSS 10 33 10 µA High level output voltage Type B4 to B12 IOH 1 µA VDD 0 05 Type B4 IOH 4 mA Type B6 IOH 6 mA Type B8 IOH 8 mA Type B10 IOH 10 mA VOH Type B12 IOH 12 mA 2 4 V Low level output voltage Type B4 to B12 IOL 1 µA 0 05 Type B4 IOL 4 mA Type B6 IOL 6 mA Type B8 IOL 8 mA ...

Page 516: ...4 VDD V High level input current Input buffer 10 10 IIH Input buffer with pull down VIN VDD 10 33 60 µA Low level input current IIL Input buffer VIN VSS 10 33 10 µA High level output voltage Type B4 to B12 IOH 1 µA VDD 0 05 Type B4 IOH 4 mA Type B6 IOH 6 mA Type B8 IOH 8 mA Type B10 IOH 10 mA VOH Type B12 IOH 12 mA 0 73 VDD V Low level output voltage Type B4 to B12 IOL 1 µA 0 05 Type B4 IOL 4 mA T...

Page 517: ...ng threshold CMOS 0 24 VDD V High level input current Input buffer 10 10 IIH Input buffer with pull down VIN VDD 10 25 50 µA Low level input current IIL Input buffer VIN VSS 10 10 µA High level output voltage Type B4 to B12 IOH 1 µA VDD 0 05 Type B4 IOH 4 mA Type B6 IOH 6 mA Type B8 IOH 8 mA Type B10 IOH 10 mA VOH Type B12 IOH 12 mA 0 73 VDD V Low level output voltage Type B4 to B12 IOL 1 µA 0 05 ...

Page 518: ...tics Symbol Parameter Condition Min Max Unit VIH High level input voltage 2 5 V VIL Low level input voltage 0 8 V IIH High level input current Vin 3 3V 10 10 µA IIL Low level input current Vin 0 0V 10 10 µA VOH Static Output High 15K to GND 2 8 3 6 V VOL Static Output Low 1 5K to 3 6V 0 3 V ...

Page 519: ...ock input is from the XTIpll pin Figure 25 1 XTIpll Clock Timing Diagram tEXTHIGH VIH 1 2 VDD VIL VIL VIH VIH 1 2 VDD tEXTLOW tEXTCYC NOTE Clock input is from the EXTCLK pin Figure 25 2 EXTCLK Clock Input Timing Diagram HCLK internal EXTCLK tEX2HC Figure 25 3 EXTCLK HCLK in case when EXTCLK is used without the PLL ...

Page 520: ...RISC MICROPROCESSOR ELECTRICAL DATA 25 9 HCLK internal SCLK CLKOUT HCLK tHC2CK tHC2SCLK Figure 25 4 HCLK CLKOUT SCLK in case when EXTCLK is used EXTCLK tRESW nRESET Figure 25 5 Manual Reset Input Timing Diagram ...

Page 521: ...O output MCU operates by XTIpll or EXTCLK clcok Clock Disable tPLL FCLK is new frequency Power PLL can operate after OM 3 2 is latched PLL is configured by S W first time VCO is adapted to new clock frequency FCLK tRST2RUN Figure 25 6 Power On Oscillation Setting Timing Diagram ...

Page 522: ...R ELECTRICAL DATA 25 11 X TIpll V C O O utput C lock D isable F C L K S everal slow clocks X TIpll or E X TC LK P ow er_O F F m ode is initiated tO S C 2 E X TC LK Figure 25 7 Sleep Mode Return Oscillation Setting Timing Diagram ...

Page 523: ...nOE DATA ADDR nBEx tRCD tROD tROD tRCD Tacc tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH 1 Figure 25 8 ROM SRAM Burst READ Timing Diagram I Tacs 0 Tcos 0 Tacc 2 Toch 0 Tcah 0 PMC 0 ST 0 DW 16bit ...

Page 524: ...TA ADDR nBEx tRCD tROD tROD tRCD tRBED tRBED Tacc tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH Figure 25 9 ROM SRAM Burst READ Timing Diagram II Tacs 0 Tcos 0 Tacc 2 Toch 0 Tcah 0 PMC 0 ST 1 DW 16bit ...

Page 525: ...32442B RISC MICROPROCESSOR 25 14 HCLK nGS nOE ADDR tXnBRQS XnBREQ tXnBRQH XnBACK HZ HZ HZ tXnBACKD tXnBACKD tHZD tHZD tHZD Figure 25 10 External Bus Request in ROM SRAM Cycle Tacs 0 Tcos 0 Tacc 8 Toch 0 Tcah 0 PMC 0 ST 0 ...

Page 526: ...OPROCESSOR ELECTRICAL DATA 25 15 HCLK nGCSx tRAD Tacs nOE Tcos DATA ADDR nWBEx 1 Toch Tcah tRCD tROD tRDS tRDH tROD tRCD tRAD Tacc Figure 25 11 ROM SRAM READ Timing Diagram I Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2 PMC 0 ST 0 ...

Page 527: ...ISC MICROPROCESSOR 25 16 HCLK nGCSx tRAD Tacs nOE Tcos DATA ADDR nBEx Toch Tcah tRCD tROD tRDS tRDH tROD tRCD tRAD tRBED tRBED Tacc Figure 25 12 ROM SRAM READ Timing Diagram II Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2cycle PMC 0 ST 1 ...

Page 528: ...LECTRICAL DATA 25 17 HCLK nGCSx tRAD Tacs nWE Tcos DATA ADDR nWBEx Toch Tcah tRCD tRWD tRDD tRWD tRCD tRAD Tcos Toch tRWBED tRWBED Tacc tRDD Figure 25 13 ROM SRAM WRITE Timing Diagram I Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2 PMC 0 ST 0 ...

Page 529: ... RISC MICROPROCESSOR 25 18 HCLK nGCSx tRAD Tacs nWE Tcos DATA ADDR nBEx Toch Tcah tRCD tRWD tRDD tRWD tRCD tRAD tRBED tRBED Tacc tRDD Figure 25 14 ROM SRAM WRITE Timing Diagram II Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2 PMC 0 ST 1 ...

Page 530: ... NOTE The status of nWait is checked at Tacc 1 cycle sampling nWait Figure 25 15 External nWAIT READ Timing Diagram Tacs 0 Tcos 0 Tacc 6 Toch 0 Tcah 0 PMC 0 ST 0 HCLK nGCSx nWE DATA ADDR tRDD tRDD Tacc 2cycle nWait tWS tWH Figure 25 16 External nWAIT WRITE Timing Diagram Tacs 0 Tcos 0 Tacc 4 Toch 0 Tcah 0 PMC 0 ST 0 ...

Page 531: ... Figure 25 17 Masked ROM Single READ Timing Diagram Tacs 2 Tcos 2 Tacc 8 PMC 01 10 11 HCLK nGCSx tRAD nOE DATA ADDR tRCD tROD tRDS tRDH tRAD Tacc Tpac Tpac Tpac Tpac tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH Figure 25 18 Masked ROM Consecutive READ Timing Diagram Tacs 0 Tcos 0 Tacc 3 Tpac 2 PMC 01 10 11 ...

Page 532: ...SSOR ELECTRICAL DATA 25 21 SCLK nSRAS tSAD Trp nSCAS DATA ADDR BA nBEx tSRD tSDS tSDH SCKE A10 AP nGCSx tSCSD nWE tSAD tSCD tSWD 1 Trcd tSBED Tcl Figure 25 19 SDRAM Single Burst READ Timing Diagram Trp 2 Trcd 2 Tcl 2 DW 16bit ...

Page 533: ...SRAS nSCAS ADDR BA nBEx tXnBRQH tXnBRQS SCKE A10 AP nGCSx nWE 1 XnBREQ XnBACK EXTCLK tXnBACKD tXnBACKD HZ HZ HZ HZ HZ HZ HZ HZ HZ tHZD tHZD tHZD tHZD tHZD tHZD tHZD tHZD tHZD tXnBRQL Figure 25 20 External Bus Request in SDRAM Timing Diagram Trp 2 Trcd 2 Tcl 2 ...

Page 534: ...C32442B RISC MICROPROCESSOR ELECTRICAL DATA 25 23 SCLK nSRAS tSAD nSCAS DATA ADDR BA nBEx tSRD SCKE A10 AP nGCSx tSCSD nWE tSAD tSCD tSWD 1 tSAD tSCSD tSRD HZ 1 tSWD Figure 25 21 SDRAM MRS Timing Diagram ...

Page 535: ...ROCESSOR 25 24 SCLK nSRAS tSAD Trp nSCAS DATA ADDR BA nBEx tSRD tSDS tSDH SCKE A10 AP nGCSx tSCSD nWE tSAD tSCD tSWD 1 tSAD tSAD Trcd tSCSD tSRD tSCSD tSAD tSAD tSBED Tcl Figure 25 22 SDRAM Single READ Timing Diagram I Trp 2 Trcd 2 Tcl 2 ...

Page 536: ...CAL DATA 25 25 SCLK nSRAS tSAD Trp nSCAS DATA ADDR BA nBEx tSRD tSDS tSDH SCKE A10 AP nGCSx tSCSD nWE tSAD tSCD tSWD 1 tSAD tSAD Trcd tSCSD tSRD tSCSD tSAD tSAD tSBED Tcl Figure 25 23 SDRAM Single READ Timing Diagram II Trp 2 Trcd 2 Tcl 3 ...

Page 537: ...RAS tSAD Trp nSCAS DATA ADDR BA nBEx tSRD SCKE A10 AP nGCSx tSCSD nWE tSAD tSCD tSWD 1 tSAD tSCSD tSRD 1 1 HZ Trc NOTE Before executing an auto self refresh command all the banks must be in idle state Figure 25 24 SDRAM Auto Refresh Timing Diagram Trp 2 Trc 4 ...

Page 538: ...SSOR ELECTRICAL DATA 25 27 SCLK nSRAS tSAD Trp nSCAS DATA ADDR BA nBEx tSRD tSDS tSDH SCKE A10 AP nGCSx tSCSD nWE tSAD tSCD tSWD 1 Trcd tSBED Tcl Tcl Tcl Figure 25 25 SDRAM Page Hit Miss READ Timing Diagram Trp 2 Trcd 2 Tcl 2 ...

Page 539: ...p nSCAS DATA ADDR BA nBEx tSRD SCKE A10 AP nGCSx tSCSD nWE tSAD tSCD tSWD tSAD tSCSD tSRD 1 1 HZ Trc tCKED HZ 1 1 1 1 1 tCKED NOTE Before executing an auto self refresh command all the banks must be in idle state Figure 25 26 SDRAM Self Refresh Timing Diagram Trp 2 Trc 4 ...

Page 540: ...TRICAL DATA 25 29 SCLK nSRAS tSAD Trp nSCAS DATA ADDR BA nBEx tSRD tSDD tSDD SCKE A10 AP nGCSx tSCSD nWE tSAD tSCD tSWD 1 tSAD tSAD Trcd tSCSD tSRD tSCSD tSAD tSAD tSBED tSWD Figure 25 27 SDRAM Single Write Timing Diagram Trp 2 Trcd 2 ...

Page 541: ...32442B RISC MICROPROCESSOR 25 30 SCLK nSRAS tSAD Trp nSCAS DATA ADDR BA nBEx tSRD tSDD tSDD SCKE A10 AP nGCSx tSCSD nWE tSAD tSCD tSWD 1 Trcd tSBED Figure 25 28 SDRAM Page Hit Miss Write Timing Diagram Trp 2 Trcd 2 Tcl 2 ...

Page 542: ...nXDACK Read Write Min 3SCLK Figure 25 29 External DMA Timing Diagram Handshake Single transfer VSYNC HSYNC VDEN Tf2hsetup Tf2hhold Tvspw Tvbpd Tvfpd HSYNC VCLK VD VDEN LEND Tl2csetup Tvclkh Tvclk Tvclkl Tvdhold Tvdsetup Tve2hold Tle2chold Tlewidth Figure 25 30 TFT LCD Controller Timing Diagram ...

Page 543: ...ROPROCESSOR 25 32 IISSCLK tLRCK IISLRCK out tSDO IISLRCK out tSDIH tSDIS IISSDI in Figure 25 31 IIS Interface Timing Diagram tSTOPH tSTARTS tSDAS tSDAH tBUF tSCLHIGH tSCLLOW fSCL IICSCL IICSDA Figure 25 32 IIC Interface Timing Diagram ...

Page 544: ...out tSDCH tSDCS tSDDD SDCMD in tSDDH tSDDS SDDATA 3 0 in SDDATA 3 0 out Figure 25 33 SD MMC Interface Timing Diagram SPICLK tSPIMOD tSPISIH tSPISIS tSPISOD tSPIMIH tSPIMIS SPIMOSI MO SPIMOSI SI SPIMISO SO SPIMISO MI Figure 25 34 SPI Interface Timing Diagram CPHA 1 CPOL 1 ...

Page 545: ...E DATA 7 0 DATA 7 0 HCLK CLE nFWE tCLED tCLED tWED tWED tWDS tWDH tALED tWED tWDS tALED tWED tWDH TACLS Figure 25 35 NAND Flash Address Command Timing Diagram HCLK nFWE TWRPH0 TWRPH1 DATA 7 0 HCLK nFRE TWRPH0 TWRPH1 DATA 7 0 tWED tWED tWDH tWED tWED tRDS tRDH tWDS WDATA RDATA Figure 25 36 NAND Flash Timing Diagram ...

Page 546: ...SC32442B RISC MICROPROCESSOR ELECTRICAL DATA 25 35 PCLK VSYNC PCLK HREF PCLK DATA TssHref ThHref TssVsync ThVsync TssData ThData Figure 25 37 Camera Timing Diagram ...

Page 547: ...ternal clock input cycle time tEXTCYC 15 0 ns External clock input low level pulse width tEXTLOW 7 ns External clock to HCLK without PLL tEX2HC 3 7 ns HCLK internal to CLKOUT tHC2CK 3 9 ns HCLK internal to SCLK tHC2SCLK 1 2 ns External clock input high level pulse width tEXTHIGH 4 ns Reset assert time after clock stabilization tRESW 10 XTIpll or EXTCLK PLL Lock Time tPLL 300 µS Sleep mode return o...

Page 548: ...a Delay tRDD 2 7 ns ROM SRAM External Wait Setup Time tWS 4 ns ROM SRAM External Wait Hold Time tWH 0 ns ROM SRAM Write Enable Delay tRWD 3 7 ns Table 25 7 Memory Interface Timing Constants VDDiarm 1 4V 0 05 V VDDi 1 2V 0 05 V TA 25 to 85 C VDDMOP 1 8V 0 1V 100MHz CL 50pF Parameter Symbol Min Typ Max Unit SDRAM Address Delay TSAD 1 60 5 17 ns SDRAM Chip Select Delay TSCSD 1 29 4 42 ns SDRAM Row Ac...

Page 549: ... ns SDRAM Clock Enable Delay Tcked 1 26 3 81 ns note This AC parameter is for 500M 125MHz case At that time VDDiarm VDDi should have separated voltage domain VDDiarm 1 7V 0 05 V VDDi 1 2V 0 05 V VDDiarm 1 4V 0 05 V VDDi 1 2V 0 05 V TA 25 to 85 C VDDMOP 1 8V 0 1V 133MHz CL 25pF Parameter Symbol Min Typ Max Unit SDRAM Address Delay TSAD 1 02 5 17 ns SDRAM Chip Select Delay TSCSD 1 11 4 42 ns SDRAM R...

Page 550: ...ns External Bus Request Hold Time tXnBRQH 1 ns External Bus Ack Delay tXnBACKD 4 10 ns HZ Delay tHZD 2 6 ns Table 25 9 DMA Controller Module Signal Timing Constants VDDiarm 1 7V 0 05 V VDDi 1 2V 0 05 V TA 25 to 85 C VEXT 3 3V 0 3V Parameter Symbol Min Typ Max Unit External Request Setup tXRS 5 ns Access To Ack Delay During Low Transition tCADL 3 8 ns Access To Ack Delay During High Transition tCAD...

Page 551: ... 0 5 Pvclk VDEN Setup To VCLK Falling Edge Tde2csetup 0 5 Pvclk VDEN Hold From VCLK Falling Edge Tde2chold 0 5 Pvclk VD Setup To VCLK Falling Edge Tvd2csetup 0 5 Pvclk VD Hold From VCLK Falling Edge Tvd2chold 0 5 Pvclk VSYNC Setup To HSYNC Falling Edge Tf2hsetup HSPW 1 Pvclk VSYNC Hold From HSYNC Falling Edge Tf2hhold HBPD HFPD HOZVAL 3 Pvclk NOTES 1 HSYNC period 2 VCLK period Table 25 11 IIS Cont...

Page 552: ...TOPH std 4 0 fast 0 6 µs NOTES Std means Standard Mode and fast means Fast Mode 1 The IIC data hold time tSDAH is minimum 0ns IIC data hold time is minimum 0ns for standard fast bus mode in IIC specification v2 1 Please check whether the data hold time of your IIC device is 0 nS or not 2 The IIC controller supports only IIC bus device standard fast bus mode and not C bus device Table 25 13 SD MMC ...

Page 553: ...15 ns SPI MISO Master Input Hold Time tSPIMIH 1 ns Table 25 15 USB Electrical Specifications VDDiarm 1 7V 0 05 V VDDi 1 2V 0 05 V TA 25 to 85 C VEXT 3 3V 0 3V Parameter Symbol Condition Min Max Unit Supply Current Suspend Device ICCS 10 µA Leakage Current Hi Z state Input Leakage ILO 0V VIN 3 3V 10 10 µA Input Levels Differential Input Sensitivity VDI D D 0 2 V Differential Common Mode Range VCM I...

Page 554: ...al Crossover Voltage Vcrs 1 3 2 0 V Drive Output Resistance Zdrv Steady state drive 28 44 ohm Table 25 17 USB Low Speed Output Buffer Electrical Characteristics VDDiarm 1 7V 0 05 V VDDi 1 2V 0 05 V TA 25 to 85 C VEXT 3 3V 0 3V Parameter Symbol Condition Min Max Unit Driver Characteristics 75 Rising Time TR CL 50pF CL 350pF 300 75 Falling Time TF CL 50pF CL 350pF 300 ns Rise Fall Time Matching Trfm...

Page 555: ...ble Delay tRED 6 7 ns NFCON Write Data Setup Time tWDS 7 5 ns NFCON Write Data Hold Time tWDH 6 3 ns NFCON Read Data Setup Requirement Time tRDS 4 ns NFCON Read Data Hold Requirement Time tRDH 0 3 ns Table 25 19 Camera Controller Module Signal Timing Constants VDDiarm 1 7V 0 05 V VDDi 1 2V 0 05 V TA 25 to 85 C VEXT 3 3V 0 3V Parameter Symbol Min Typ Max Units VSYNC input Setup time TssVsync 3 ns V...

Page 556: ...EL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS AS IS BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND 1 For updates or additional information about Samsung products contact your nearest Samsung office 2 Samsung products are not intended for use in life support critical care medical safety equipment or similar ...

Page 557: ... Final History Initial issue 2Gb NAND Flash A Die_ Ver 0 3 512Mb Mobile SDRAM C Die_Ver 1 0 Mobile SDRAM Changed default driver strength from half to full in page 50 NAND Flash _Ver 1 0 1 8V device supports Copy Back Program Mobile SDRAM _Ver 1 1 Correcting typo error Finalized Draft Date Jun 28 2006 Jul 14 2006 Dec 11 2006 Note For more detailed features and specifications including FAQ please re...

Page 558: ...ith the use of system clock and I O transactions are possible on every clock cycle Range of operating frequencies programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications The K5D2G13ACM is suitable for use in data memory of mobile communication system to reduce not only mount area but al...

Page 559: ...DQM3d CASd A2d A7d A10d BA0d DQ2d DQ0d DQ3d DQ8d DQ7d DQ11d DQ12d NC NC VSSd VDDd VDDQd NC NC VSSd VSSd VDDd VDDd NC NC VDDQd VSSQd VDDd VSSd NC NC NC VDDQd VSSQd VDDQd VSSQd VDDQd VSSQd NC VDDQd VSSQd VDDQd VSSQd VSSQd VDDQd NC NC VSSQd NC NC NC CSd WEd REn WEn CLEn DQM0d A1d A3d A6d VDDd VDDQd VSSQd DQ30d DQ29d DQ25d DQ31d DQ23d DQ24d DQ21d DQ19d DQ17d DQ14d VSSd VCCn VSSn VCCn DQ28d DQ27d DQ26d...

Page 560: ...IPTION Pin Name Pin Function Mobile SDRAM CLKd System Clock CKEd Clock Enable CSd Chip Select RASd Row Address Strobe CASd Column Address Strobe WEd Write Enable A0d A12d Address Input BA0d BA1d Bank Address Input DQM0d DQM3d Input Output Data Mask DQ8d DQ31d Data Input Output VDDd Power Supply VDDQd Data Out Power VSSd Ground VSSQd DQ Ground Pin Name Pin Function NAND Flash CEn Chip Enable REn Re...

Page 561: ...r 2006 6 MCP MEMORY FUNCTIONAL BLOCK DIAGRAM WPn CLEn WEn REn R Bn CEn DQ0 IO0 to DQ7 IO7 CSv CASd RASd CKEd WEd CLKd A0d A12d DQM0d DQM3d BA0d BA1d ALEn 2Gb NAND Flash Memory DQ8 to DQ31 512Mb Mobile SDRAM VDDd VDDQd VCCn VSSn VSSd VSSQd ...

Page 562: ...K5D2G13ACM D075 Revision 1 0 December 2006 7 MCP MEMORY 2Gb 256Mb x8 NAND Flash Memory A Die ...

Page 563: ...0 A21 A22 A23 A24 A25 A26 A27 5th Cycle A28 L L L L L L L VCC X Buffers Command I O Buffers Latches Latches Decoders Y Buffers Latches Decoders Register Control Logic High Voltage Generator Global Buffers Output Driver VSS A12 A28 A0 A11 Command CE RE WE CLE WP I 0 0 I 0 7 VCC VSS 128K Pages 2 048 Blocks 2K Bytes 8 bit 64 Bytes 1 Block 64 Pages 128K 4k Byte I O 0 I O 7 1 Page 2K 64 Bytes 1 Block 2...

Page 564: ...r commands like page read and block erase and page program require two cycles one cycle for setup and the other cycle for execution The 264M byte physical space requires 29 addresses thereby requiring five cycles for addressing 2 cycles of column address 3 cycles of row address in that order Page Read and Page Program need the same five address cycles following the required command input In Block ...

Page 565: ...VOL IOL 100µA 0 1 Output Low Current R B IOL R B VOL 0 4V 3 4 mA RECOMMENDED OPERATING CONDITIONS Voltage reference to GND TA 25 to 85 C Parameter Symbol Min Typ Max Unit Supply Voltage VCC 1 7 1 8 1 95 V Supply Voltage VSS 0 0 0 V ABSOLUTE MAXIMUM RATINGS NOTE 1 Minimum DC voltage is 0 6V on input output pins During transitions this level may undershoot to 2 0V for periods 30ns Maximum DC voltage...

Page 566: ...ock address is guaranteed to be a valid block up to 1K program erase cycles with 1bit 512Byte ECC 3 The number of valid block is on the basis of single plane operations and this may be decreased with two plane operations Parameter Symbol Min Typ Max Unit 2Gb NVB 2 008 2 048 Blocks AC TEST CONDITION TA 25 to 85 C Vcc 1 7 1 95V unless otherwise noted Parameter Value Input Pulse Levels 0V to Vcc Inpu...

Page 567: ...lse Width tWP 25 ns ALE Setup Time tALS 1 25 ns ALE Hold Time tALH 10 ns Data Setup Time tDS 1 20 ns Data Hold Time tDH 10 ns Write Cycle Time tWC 45 ns WE High Hold Time tWH 15 ns Address to Data Loading Time tADL 2 100 ns Program Erase Characteristics NOTE 1 Typical value is measured at Vcc 3 3V TA 25 C Not 100 tested 2 Typical program time is defined as the time within which more than 50 of the...

Page 568: ...tRR 20 ns RE Pulse Width tRP 25 ns WE High to Busy tWB 100 ns Read Cycle Time tRC 45 ns RE Access Time tREA 30 ns CE Access Time tCEA 45 ns RE High to Output Hi Z tRHZ 100 ns CE High to Output Hi Z tCHZ 30 ns CE High to ALE or CLE Don t Care tCSD 10 ns RE High to Output Hold tRHOH 15 ns RE Low to Output Hold tRLOH ns CE High to Output Hold tCOH 15 ns RE High Hold Time tREH 15 ns Output Hi Z to RE ...

Page 569: ...ase cycles with 1bit 512Byte ECC All device locations are erased FFh except locations where the initial invalid block s information is written prior to shipping The ini tial invalid block s status is defined by the 1st byte in the spare area Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non FFh data at the column address of 2048 Since the initial invalid blo...

Page 570: ...ock replacement should be done Because program status fail during a page program does not affect the data of the other pages in the same block block replacement can be executed with a page sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block In case of Read ECC must be employed To improve the efficiency of memory space i...

Page 571: ...m the Error Page Read Completed Yes NAND Flash Technical Notes Continued Write 30h Block Replacement Step1 When an error happens in the nth page of the Block A during erase or program operation Step2 Copy the data in the 1st n 1 th page to the same location of another free block Block B Step3 Then copy the nth page data of the Block A in the buffer memory to the nth page of the Block B Step4 Do no...

Page 572: ...1 st sector H area 4 th sector Main Field 2 048 Byte 16 Byte G area 3 rd sector 16 Byte F area 2 nd sector 16 Byte E area 1 st sector 16 Byte B area 512 Byte 2 nd sector C area 512 Byte 3 rd sector D area 512 Byte 4 th sector Spare Field 64 Byte Table 2 Definition of the 528 Byte Sector Sector Main Field Column 0 2 047 Spare Field Column 2 048 2 111 Area Name Column Address Area Name Column Addres...

Page 573: ...flexible In addition for voice or audio applications which use slow cycle time on the order of µ seconds de activating CE during the data loading and serial access would provide significant savings in power consumption Figure 4 Program Operation with CE don t care CE WE tWP tCH tCS Address 5Cycles 80h Data Input CE CLE ALE WE Data Input CE don t care 10h tCEA out tREA CE RE I O0 7 Figure 5 Read Op...

Page 574: ...TE Device I O DATA ADDRESS I Ox Data In Out Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 2Gb I O 0 I O 7 2 112byte A0 A7 A8 A11 A12 A19 A20 A27 A28 I Ox CE WE CLE ALE Col Add1 tCS tWC tWP tALS tDS tDH tALH tALS tWH tWC tWP tDS tDH tALH tALS tWH tWC tWP tDS tDH tALH tALS tWH tDS tDH tWP I Ox Col Add2 Row Add1 Row Add2 tWC tWH tALH tALS tDS tDH Row Add3 tALH tCLS ...

Page 575: ... tWP I Ox Serial Access Cycle after Read CLE L WE H ALE L RE CE R B Dout Dout Dout tRC tREA tRR tRHOH tREA tREH tREA tCOH tRHZ I Ox tCHZ tRHZ NOTES Transition is measured at 200mV from steady state voltage with load This parameter is sampled and not 100 tested tRLOH is valid when frequency is higher than 33MHz tRHOH starts to be valid when frequency is lower than 33MHz ...

Page 576: ...CLS I Ox tCHZ tRHZ tCS RE CE R B I Ox tRR tCEA tREA tRP tREH tRC tRHZ tCHZ Serial Access Cycle after Read EDO Type CLE L WE H ALE L tRHOH tCOH tRLOH Dout Dout tREA NOTES Transition is measured at 200mV from steady state voltage with load This parameter is sampled and not 100 tested tRLOH is valid when frequency is higher than 33MHz tRHOH starts to be valid when frequency is lower than 33MHz ...

Page 577: ...N Dout N 1 Dout N 2 Row Address Column Address tWB tAR tCHZ tR tRR tRC 30h Read Operation CE CLE R B WE ALE RE Busy 00h Col Add1 Col Add2 Row Add1 Dout N Dout N 1 Column Address Row Address tWB tAR tR tRC tRHZ tRR Dout M tWC Row Add2 30h tCLR I Ox I Ox Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Row Add3 tCOH tCLR tCSD tCSD ...

Page 578: ...andom Data Output In a Page CE CLE R B WE ALE RE Busy 00h Dout N Dout N 1 Row Address Column Address t WB t AR t R t RR 30h 05h Column Address Dout M Dout M 1 I Ox Col Add1 Col Add2 Row Add1 Row Add2 Col Add1 Col Add2 Row Add3 t CLR E0h t WHR t REA t RC t RHW ...

Page 579: ...ut Command Column Address Row Address 1 up to m Byte Serial Input Program Command Read Status Command I O0 0 Successful Program I O0 1 Error in Program tPROG tWB tWC tWC tWC I Ox Co l Add1 Col Add2 Row Add1 Row Add2 Row Add3 NOTES tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle tADL tWHR ...

Page 580: ...ut Program Command Read Status Command t PROG t WB t WC t WC 85h Random Data Input Command Column Address t WC Din J Din K Serial Input I Ox Col Add1 Col Add2 Row Add1 Row Add2 Col Add1 Col Add2 Row Add3 NOTES 1 tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle t ADL 2 For EDC operation only one time random data input is possible at the same ...

Page 581: ...m t PROG t WB t WC Busy t WB t R Busy 10h Copy Back Data Input Command 35h Column Address Row Address Data 1 Data N I Ox Col Add1 Col Add2 Row Add1 Row Add2 Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Row Add3 7Bh 70h I O 1 I O 2 EDC Status 7Bh only NOTES 1 tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle t ADL 2 For EDC operation only one ...

Page 582: ...CP MEMORY Block Erase Operation CE CLE R B WE ALE RE 60h Erase Command Read Status Command I O0 1 Error in Erase D0h 70h I O 0 Busy tWB tBERS I O0 0 Successful Erase Row Address tWC Auto Block Erase Setup Command I Ox Row Add1 Row Add2 Row Add3 tWHR ...

Page 583: ...Y tWB tWC Command Dummy Din N 10h tPROG tWB I O Program Confirm Command True 81h 70h Page Row Address I Ox 1 up to 2112 Byte Data Serial Input Din M Read Status Command t DBSY typ 500ns max 1µs Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Col Add1 2 Row Add 1 2 3 2112 Byte Data A 0 A 11 Valid A 12 A 17 Fixed Low A 18 Fixed Low A 19 A 28 Fixed Low A 0 A ...

Page 584: ...triction for Two Plane Block Erase Operation CE CLE R B I O X WE ALE RE 60h Row Add1 D0h 70h I O 0 Busy t WB t BERS t WC D0h 70h Address Address Row Add1 2 3 I O 0 0 Successful Erase I O 0 1 Error in Erase Row Add2 Row Add3 A 12 A 17 Fixed Low A 18 Fixed Low A 19 A 28 Fixed Low A 12 A 17 Fixed Low A 18 Fixed High A 19 A 28 Valid 60h Row Add1 D0h Row Add2 Row Add3 Row Address t WC Block Erase Setup...

Page 585: ...30 MCP MEMORY Read ID Operation CE CLE WE ALE RE 90h Read ID Command Maker Code Device Code 00h ECh tREA Address 1cycle I Ox tAR Device Device Code 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 1 8V AAh 00h 15h 44h Device 4th cyc Code 3rd cyc 5th cyc ...

Page 586: ...mmand 90H Description 1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte Maker Code Device Code Internal Chip Number Cell Type Number of Simultaneously Programmed Pages Etc Page Size Block Size Redundant Area Size Organization Serial Access Minimum Plane Number Plane Size 3rd ID Data Description I O7 I O6 I O5 I O4 I O3 I O2 I O1 I O0 Internal Chip Number 1 2 4 8 0 0 0 1 1 0 1 1 Cell Type 2 Level Cell 4...

Page 587: ...2 MCP MEMORY 5th ID Data Description I O7 I O6 I O5 I O4 I O3 I O2 I O1 I O0 Plane Number 1 2 4 8 0 0 0 1 1 0 1 1 Plane Size w o redundant Area 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Reserved 0 0 0 ...

Page 588: ... into the data registers they may be read out in 25ns 45ns with 1 8V device cycle time by sequentially pulsing RE The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address The device may output random data in a page instead of the consecutive sequential data by writing random data output command Th...

Page 589: ...ta input command 85h Random data input may be operated multiple times regardless of how many times it is done in a page Modifying the data of a sector by Random Data Input before Copy Back Program must be performed for the whole sector and is allowed only once per each sector Any partial modification smaller than a sector corrupts the on chip EDC codes The Page Program confirm command 10h initiate...

Page 590: ...Figure 12 The internal write verification detects only errors for 1 s that are not successfully programmed to 0 s and the internal EDC checks whether there is only 1 bit error for each 528 byte sector of the source page More than 2 bit error detection is not available for each 528 byte sector The command register remains in Read Status command mode or Read EDC Status com mand mode until another va...

Page 591: ...rogram or page program mode For the user who use Copy Back without EDC there is no limitation for the random data input at the same address Two Plane Page Program Two Plane Page Program is an extension of Page Program for a single plane with 2112 byte page registers Since the device is equipped with two memory planes activating the two sets of 2112 byte page registers enables a simultaneous progra...

Page 592: ...12 A17 Fixed Low A18 Fixed High A19 A28 valid Two Plane Block Erase Basic concept of Two Plane Block Erase operation is identical to that of Two Plane Page Program Up to two blocks one from each plane can be simultaneously erased Standard Block Erase command sequences Block Erase Setup command 60h followed by three address cycles may be repeated up to twice for erasing up to two blocks Only one bl...

Page 593: ...isters enables a simultaneous program ming of two pages Data Field Spare Field Data Field Spare Field 1 2 3 3 Plane0 Plane1 Source page Target page Source page Target page 1 Read for Copy Back On Plane0 2 Read for Copy Back On Plane1 3 Two Plane Copy Back Program A0 A11 Fixed Low A12 A17 Fixed Low A18 Fixed Low A19 A28 Fixed Low A0 A11 Fixed Low A12 A17 Valid A18 Fixed High A19 A28 Valid 1 1 Note ...

Page 594: ... Fixed High A19 A28 Valid Figure 17 Two Plane Copy Back Program Operation with Random Data Input Note 1 Copy Back Program operation is allowed only within the same memory plane 2 On the same plane It s prohibited to operate copy back program from an odd address page source page to an even address page target page or from an even address page source page to an odd address page target page Therefore...

Page 595: ...0 Not Protected 1 READ EDC STATUS Read EDC status operation is only available on Copy Back Program The device contains an EDC Status Register which may be read to find out whether there is error during Read for Copy Back After writing 7Bh command to the command register a read cycle outputs the content of the EDC Status Register to the I O pins on the falling edge of CE or RE whichever occurs last...

Page 596: ...Fh to the command register When the device is in Busy state during random read program or erase mode the reset operation will abort these operations The contents of memory cells being altered are no longer valid as the data will be partially programmed or erased The command register is cleared to wait for the next command and the Status Register is cleared to value C0h when WP is high If the devic...

Page 597: ... Or tied Because pull up resistor value is related to tr R B and current drain during busy ibusy an appropriate value can be obtained with the following reference chart Fig 20 Its value can be determined by the following guidance VCC R B open drain output Device GND Rp Figure 19 Rp vs tr tf Rp vs ibusy ibusy Busy Ready Vcc VOH tf tr VOL 1 8V device VOL 0 1V VOH VCC 0 1V CL tr tf s Ibusy A Rp ohm I...

Page 598: ...enever Vcc is below about 1 1V WP pin provides hardware protection and is recommended to be kept at VIL during power up and power down A recovery time of minimum 100µs is required before internal circuit gets ready for any command sequences as shown in Figure 21 The two step command sequence for program erase provides additional software protection Figure 21 AC Waveforms for Power Transition VCC W...

Page 599: ...K5D2G13ACM D075 Revision 1 0 December 2006 44 MCP MEMORY 512Mb 16Mb x32 Mobile SDRAM C Die ...

Page 600: ...ense AMP Output Buffer I O Control Column Decoder Latency Burst Length Programming Register Address Register Row Buffer Refresh Counter Row Decoder Col Buffer LRAS LCBR LCKE LRAS LCBR LWE LDQM CLK CKE CS RAS CAS WE DQM LWE LDQM DQi CLK ADD LCAS LWCBR 4M x 32 4M x 32 Timing Register FUNCTIONAL BLOCK DIAGRAM ...

Page 601: ...ge VIL 0 3 0 0 3 V 3 Output logic high voltage VOH VDDQ 0 2 V IOH 0 1mA Output logic low voltage VOL 0 2 V IOL 0 1mA Input leakage current ILI 2 2 uA 4 CAPACITANCE VDD 1 8V TA 23 C f 1MHz VREF 0 9V 50 mV Pin Symbol Min Max Unit Note Clock CCLK 1 5 3 5 pF RAS CAS WE CS CKE CIN 1 5 3 0 pF DQM CIN 1 5 3 0 pF Address CADD 1 5 3 0 pF DQ0 DQ31 COUT 2 0 4 5 pF ABSOLUTE MAXIMUM RATINGS NOTES Permanent dev...

Page 602: ...max tCC 0 3 Precharge Standby Current in non power down mode ICC2N CKE VIH min CS VIH min tCC 10ns Input signals are changed one time during 20ns 10 mA ICC2NS CKE VIH min CLK VIL max tCC Input signals are stable 1 Active Standby Current in power down mode ICC3P CKE VIL max tCC 10ns 6 mA ICC3PS CKE CLK VIL max tCC 3 Active Standby Current in non power down mode One Bank Active ICC3N CKE VIH min CS ...

Page 603: ...Z0 50Ω Figure 2 AC Output Load Circuit Figure 1 DC Output Load Circuit AC OPERATING TEST CONDITIONS VDD 1 7 1 95 V TA 25 85 C Parameter Value Unit AC input levels Vih Vil 0 9 x VDDQ 0 2 V Input timing measurement reference level 0 5 x VDDQ V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 0 5 x VDDQ V Output load condition See Figure 2 ...

Page 604: ...auto precharge and read burst stop Parameter Symbol 133Mhz CL3 Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 22 5 ns 1 Row precharge time tRP min 22 5 ns 1 Row active time tRAS min 50 ns 1 tRAS max 100 us Row cycle time tRC min 72 5 ns 1 Last data in to row precharge tRDL min 15 ns 2 Last data in to Active delay tDAL min tRDL tRP Last data in to new col addres...

Page 605: ...is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Parameter Symbol 133Mhz CL3 Unit Note Min Max CLK cycle time CAS latency 3 tCC 7 5 1000 ns 1 CLK to valid output delay CAS latency 3 tSAC 6 ns 1 2 Output data hold time CAS latency 3 tOH 2 5 ns 2 CLK high pulse width tCH 2 5 ns 3 CLK low pulse width tCL 2 5 ns 3 Input setup time tS...

Page 606: ...op command is valid at every burst length 7 DQM sampled at the positive going edge of CLK masks the data in at that same CLK in write operation Write DQM latency is 0 but in read operation it makes the data out Hi Z state after 2 CLK cycles Read DQM latency is 2 COMMAND CKEn 1 CKEn CS RAS CAS WE DQM BA0 1 A10 AP A12 11 A9 A0 Note Register Mode Register Set H X L L L L X OP CODE 1 2 Refresh Auto Re...

Page 607: ...le Bit 1 1 1 Reserved 1 1 1 Full Page 3 Reserved Register Programmed with Normal MRS Address BA0 BA1 A12 A10 AP A9 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function 0 Setting for Normal MRS RFU 1 W B L Test Mode CAS Latency BT Burst Length NOTES 1 RFU Reserved for future use should stay 0 during MRS cycle 2 If A9 is high during MRS cycle Burst Read Single Bit Write function will be enabled 3 Full Page Length ...

Page 608: ...l MRS For operating with DS or PASR set DS or PASR mode in EMRS setting stage In order to adjust another mode in the state of DS or PASR mode additional EMRS set is required but power up sequence is not needed again at this time In that case all banks have to be in idle state prior to adjusting EMRS set BA0 0 BA1 0 BA0 0 BA1 0 BA0 1 BA1 1 BA0 1 BA1 1 BA0 0 BA1 1 BA0 1 BA1 1 BA0 0 BA1 0 BA0 1 BA1 0...

Page 609: ... 0 1 1 1 3 0 1 2 3 2 1 0 2 BURST LENGTH 8 Initial Address Sequential Interleave A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 ...

Page 610: ... The 8 bit column addresses are latched along with CAS WE and BA0 BA1 during read or write command BANK ADDRESSES BA0 BA1 In case x 16 This Mobile SDR SDRAM is organized as four independent banks of 2 097 152 words x 16 bits memory arrays The BA0 BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation The bank addresses BA0 BA1 are latched at ...

Page 611: ...on The bank addresses BA0 BA1 are latched at bank active read write mode register set and precharge operations In case x 16 2 CS This Mobile SDR SDRAM is organized as two chips which have four independent banks of 4 194 304 words x 16 bits memory arrays The BA0 BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation The bank addresses BA0 BA1 ...

Page 612: ...ilar to OE during read operation and inhibits writing during write operation The read latency is two cycles from DQM and zero cycle for write which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle DQM operation is synchronous with the clock The DQM signal is important during burst interruptions of write with read or precharge in the Mobile SDR...

Page 613: ...e same command and clock cycle requirements during operation as long as all banks are in the idle state A0 A2 are used for partial self refresh Low on BA0 and High on BA1 are used for EMRS All the other address pins except A0 A2 BA1 BA0 must be set to low for proper EMRS operation Refer to the table for specific codes BANK ACTIVATE The bank activate command is used to select a random row in an idl...

Page 614: ...s are in idle state PRECHARGE The precharge operation is performed on an active bank by asserting low on CS RAS WE and A10 AP with valid BA0 BA1 of the bank to be precharged The precharge command can be asserted anytime after tRAS min is satisfied from the bank active command in the desired bank tRP is defined as the minimum number of clock cycles required to complete row precharge is calculated b...

Page 615: ...generated to reduce power consumption The self refresh mode is entered from all banks idle state by asserting low on CS RAS CAS and CKE with high on WE Once the self refresh mode is entered only CKE state being low matters all the other inputs including the clock are ignored in order to remain in the self refresh mode The self refresh is exited by restarting the external clock and then asserting h...

Page 616: ...rite BL 4 CLK CMD CKE Internal CLK DQ CL2 DQ CL3 WR D0 D1 D2 D3 D0 D1 D2 D3 Not Written Suspended Dout 2 Clock Suspended During Read BL 4 CLK CMD CKE Internal CLK DQ CL2 DQ CL3 RD Masked by CKE Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Masked by CKE 1 Write Mask BL 4 2 Read Mask BL 4 CLK CMD DQM DQ CL2 DQ CL3 CLK CMD DQM DQ CL2 DQ CL3 WR Masked by CKE Masked by CKE D0 D1 D3 D0 D1 D3 RD Q0 Q2 Q3 Q1 Q2 Q3 DQM to Data...

Page 617: ...d write is to stopped by CAS access 2 tCCD CAS to CAS delay 1CLK 3 tCDL Last data in to new column address delay 1CLK DQ CL2 DQ CL3 3 CAS Interrupt I 1 Read interrupted by Read BL 4 1 2 Write interrupted by Write BL 2 CLK CMD ADD RD RD A B 3 Write interrupted by Read BL 2 QA0 QB0 QB1 QB1 QB3 QA0 QB0 QB1 QB1 QB3 CLK CMD ADD DQ WR WR A B DA0 DB0 DB1 CLK CMD ADD DQ CL2 DQ CL3 WR RD A B DA0 QB0 QB1 DA...

Page 618: ...Hi Z 4 CAS Interrupt II Read Interrupted by Write DQM ii CMD DQM a CL 2 BL 4 i CMD DQ CLK DQM DQ iii CMD DQM DQ iv CMD DQM DQ b CL 3 BL 4 CLK i CMD DQM DQ ii CMD DQM DQ iii CMD DQM DQ iv CMD DQM DQ v CMD DQ DQM RD WR D0 D1 D2 D3 RD WR D0 D1 D2 D3 RD WR D0 D1 D2 D3 RD WR Q0 D0 D1 D2 D3 RD WR D0 D1 D2 D3 RD WR D0 D1 D2 D3 RD WR D0 D1 D2 D3 RD WR D0 D1 D2 D3 RD WR D0 D1 D2 D3 Q0 ...

Page 619: ... 3 The row active command of the precharge bank can be issued after tRP from this point The new read write command of other activated bank can be issued from this point At burst read write with auto precharge CAS interrupt of the same bank is illegal 4 tDAL defined Last data in to Active delay SAMSUNG can support tDAL tRDL tRP Auto Precharge Starts 3 2 3 2 5 Write Interrupted by Precharge DQM 6 Pr...

Page 620: ...or CAS latency 2 3 respectively 4 PRE All banks precharge is necessary MRS can be issued only at all banks precharge state A B A B 4 tRP 2CLK tRDL1 tBDL 2 8 Burst Stop Interrupted by Precharge 9 MRS 1 Normal Write D0 D1 D2 2 Write Burst Stop BL 8 CMD DQ CLK DQM BL 4 tRDL 2CLK WR PRE CLK CMD DQM DQ WR STOP D0 D1 D2 D3 3 Read Interrupted by Precharge BL 4 CLK CMD DQ CL2 DQ CL3 RD PRE Q0 Q1 Q0 Q1 4 R...

Page 621: ...8V CLK A Self Refresh command is defined by having CS RAS CAS and CKE held low with WE high at the rising edge of the clock Once the self Refresh command is initiated CKE must be held low to keep the device in Self Refresh mode After 1 clock cycle from the self refresh command all of the external control signals including system clock CLK can be disabled except CKE The clock is internally disabled...

Page 622: ... At MRS A2 1 0 011 Full Page At MRS A2 1 0 111 Wrap around mode infinite burst length should be stopped by burst stop RAS interrupt or CAS interrupt Special MODE BRSW At MRS A9 1 Read burst 1 2 4 8 full page write Burst 1 At auto precharge of write tRAS should not be violated Random MODE Burst Stop tBDL 1 Valid DQ after burst stop is 1 2 for CAS latency 2 3 respectively Using burst stop command an...

Page 623: ...P Term burst New Read Determine AP L H L L BA CA A10 AP Term burst New Write Determine AP 3 L L H H BA RA ILLEGAL 2 L L H L BA A10 AP Term burst Precharge timing for Reads L L L X X X ILLEGAL Write H X X X X X NOP Continue Burst to End Row Active L H H H X X NOP Continue Burst to End Row Active L H H L X X Term burst Row active L H L H BA CA A10 AP Term burst New read Determine AP 3 L H L L BA CA ...

Page 624: ... A10 AP 5 Illegal if any bank is not idle Current CS RAS CAS WE BA Address Action Note Precharging H X X X X X NOP Idle after tRP L H H H X X NOP Idle after tRP L H H L X X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 AP NOP Idle after tRP 4 Row Activating L L L X X X ILLEGAL H X X X X X NOP Row Active after tRCD L H H H X X NOP Row Active after tRCD L H H L X X ILLEGAL...

Page 625: ...dle after tsRFX ABI 6 L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP Maintain Self Refresh All Banks Precharge Power Down H X X X X X X INVALID L H H X X X X Exit Power Down ABI L H L H H H X Exit Power Down ABI 7 L H L H H L X ILLEGAL 7 L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP Maintain Low Power Mode All Banks Idle H H X X X X X Refer to T...

Page 626: ...nt Bank Burst Length 4 Read Write Cycle With Auto Precharge l Burst Length 4 Read Write Cycle With Auto Precharge ll Burst Length 4 Clock Suspension DQM Operation Cycle CAS Letency 2 Burst Length 4 Read Interrupted by Precharge Command Read Burst Stop Cycle Full Page Burst Write Interrupted by Precharge Command Write Burst Stop Cycle Full Page Burst tRDL 2CLK Burst Read Single bit Write Cycle Burs...

Page 627: ...t condition for a minimum of 200us 3 Issue precharge commands for all banks of the devices 4 Issue 2 or more auto refresh commands 5 Issue a mode register set command to initialize the mode register 6 Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS For operating with DS or PASR set DS or PASR mode in EMRS setting stage In order to adjus...

Page 628: ...K Single Bit Read Write Read Cycle Same Page CAS Latency 3 Burst Length 1 HIGH Ra Ca BS BS Ra DQ Row Active Read Write Read Row Active Precharge tCC tCH tCL tRAS tRC tSH tSS Note 1 tRCD tRP tSH tSS tSH tSS tSH tSS Note 2 Note 2 3 Note 2 3 Note 2 3 Note 4 Note 2 Note 3 Note 3 Note 3 Note 4 tSS tSH tOH tSLZ tSAC tSH tSS tSH tSS Cb Cc Rb BS BS BS BS Qa Db Qc Rb Hi Z ...

Page 629: ...b 256Mb 512Mb Operation BA0 BA1 BA0 BA1 0 0 0 0 0 Disable auto precharge leave bank A active at end of burst 0 1 1 0 Disable auto precharge leave bank B active at end of burst 1 0 0 1 Disable auto precharge leave bank C active at end of burst 1 1 1 1 Disable auto precharge leave bank D active at end of burst 1 0 0 0 0 Enable auto precharge precharge bank A at end of burst 0 1 1 0 Enable auto prech...

Page 630: ... times is required to complete internal DRAM operation 2 Row precharge can interrupt burst on any cycle CAS Latency 1 number of valid output data is available after Row precharge Last valid output will be Hi Z tSHZ after the clcok 3 Ouput will be Hi Z after the end of burst 1 2 4 8 Full page bit burst BA0 DQ tRDL Note 2 Note 3 tSHZ tSAC tOH tRDL Note 3 A Bank A Bank A Bank A Bank Row Active A Bank...

Page 631: ...oid bus contention 2 Row precharge will interrupt writing Last data input tRDL before Row precharge will be written 3 DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst Input data after Row pre charge cycle will be masked internally 4 tDAL last data in to active delay is tRDL tRP BA0 DQ tRDL Note 3 A Bank A Bank A Bank A Bank Note 2 Cb tDAL N...

Page 632: ...d WE are high at the clock high going dege 2 To interrupt a burst read by row precharge both the read and the precharge banks must be the same BA0 DQ A Bank A Bank D Bank Note 2 RCc Read B Bank CBb RDd CCc CDd RBb RCc RDd QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 Row Active B Bank Row Active C Bank Row Active D Bank Precharge A Ba...

Page 633: ...e Note 1 To interrupt burst write by Row precharge DQM should be asserted to mask invalid input data 2 To interrupt burst write by Row precharge both the write and the precharge banks must be the same BA0 DQM DQ Note 1 A Bank A Bank D Bank All Banks Note 2 RAb CAa CBb RCc RDd CCc RAa RBb RCc RDd DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2 tCDL tRDL Row Active B Bank Write B Bank Row Active C...

Page 634: ...e at Different Bank Burst Length 4 HIGH RAa RAa CL 2 Row Active Read Write Read Note 1 tCDL should be met to complete write BA0 DQ A Bank A Bank D Bank B Bank Precharge A Bank CAa RDb RBc CBc RDb tCDL Note 1 Row Active D Bank Row Active B Bank QAa1 QAa0 QAa2 QAa3 QBc0 QBc1 QBc2 DDb0 DDb1 DDb2 DDb3 QAa1 QAa0 QAa2 QAa3 QBc0 QBc1 CDb RBc DDb0 DDb1 DDb2 DDb3 CL 3 CL 2 DQM Hi Z Hi Z ...

Page 635: ... Read Write command without auto precharge is issued at B Bank before A Bank auto precharge starts A Bank auto precharge will start at B Bank read command input point any command can not be issued at A Bank during tRP after A Bank auto precharge starts BA0 A Bank Auto Pre B Bank A Bank Read without Auto Precharge B Bank RBb RAc CAc CAa CBb RBb DAc0 DAc0 charge A Bank Row Active B Bank Auto Prechar...

Page 636: ... HIGH Ra Row Active Read with Note 1 Any command to A bank is not allowed in this period tRP is determined from at auto precharge start point BA0 A Bank Auto Precharge Auto Precharge Start Point Ca Rb A Bank A Bank Row Active B Bank Note1 Cb Read with Auto Precharge B Bank Auto Precharge Start Point B Bank Rb Qa1 Qa0 Qa2 Qa3 Qb1 Qb0 Qb2 Qb3 Qa1 Qa0 Qa2 Qa3 Qb1 Qb0 Qb2 Qb3 Ra CL 3 CL 2 DQM CL 3 CL ...

Page 637: ...AS BA1 A10 AP ADDR WE Don t care CLOCK Clock Suspension DQM Operation Cycle CAS Latency 2 Burst Length 4 Ra Row Active Read Write Note 1 DQM is needed to prevent bus contention BA0 DQM DQ Note 1 DQM Ca Qb0 Qb1 Dc0 Dc2 Clock Suspension Write Cb Ra tSHZ tSHZ Read Clock Suspension Write DQM Read DQM Qa1 Qa2 Qa3 Qa0 Cc Hi Z ...

Page 638: ...Qs after burst stop it is same as the case of Precharge interrupt Both cases are illustrated above timing diagram See the label A B on them But at burst write Burst stop and Precharge interrupt should be compared carefully Refer the timing diagram of Full page write burst stop cycle 3 Burst stop is valid at every burst length BA0 QAa3 A Bank CAa CAb Burst Stop Precharge A Bank DQ QAa4 A A QAa2 QAa...

Page 639: ...ted by precharge can not be written into the corresponding memory cell It is defined by AC parameter of tRDL DQM at write interrupted by precharge command is needed to prevent invalid write DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst Input data after Row pre charge cycle will be masked internally 3 Burst stop is valid at every burst le...

Page 640: ...xed to 1 regardless of programmed burst length 2 When BRSW write command with auto precharge is executed keep it in mind that tRAS should not be violated Auto precharge is executed at the burst end cycle so in the case of BRSW write command the next cycle starts the precharge BA0 A Bank CAa RCc Precharge C Bank DQ RAa Write A Bank Note 2 RBb CAb CBc CCd RBb RCc Row Active B Bank Read with Auto Pre...

Page 641: ...e 1 All banks should be in idle state prior to entering precharge power down mode 2 CKE should be set high at least 1CLK tSS prior to Row active command 3 Can not violate minimum refresh specification 64Ms BA0 BA1 DQM DQ Note 1 Power down Note 2 Ra Ca Qa0 Qa1 Qa2 Precharge Power down Read Ra tSHZ Note 2 Entry Exit Active Power down Entry Active Power down Exit tSS Note 3 tSS tSS CLOCK tSS Hi Z ...

Page 642: ... care except for CKE 3 The device remains in self refresh mode as long as CKE stays Low cf Once the device enters self refresh mode minimum tRAS is required before exit from self refresh TO EXIT SELF REFRESH MODE 4 System clock restart and be stable before returning CKE high 5 CS starts from high 6 Minimum tRC tSRFX is required after CKE going high to complete self refresh exit BA0 BA1 DQM DQ Note...

Page 643: ...S BA0 BA1 WE activation at the same clock cycle with address key will set internal mode register 2 Minimum 2 clock cycles should be met before new RAS activation 3 Please refer to Mode Register Set table 4 All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle BA0 DQM DQ Ra Auto Refresh Auto Refresh Cycle HIGH HIGH New Command Note2 Note1 Note3 tARFC Hi Z Hi ...

Page 644: ...ter Set Cycle Key EMRS New Command Note EXTENDED MODE REGISTER SET CYCLE 1 CS RAS CAS BA0 BA1 WE activation at the same clock cycle with address key will set internal mode register 2 Minimum 2 clock cycles should be met before new RAS activation 3 Please refer to Mode Register Set table BA0 DQM DQ Ra HIGH Note2 Note1 Note3 Hi Z WE ...

Page 645: ...VIEW A1 14 00 0 10 14 00 0 10 0 80 x 16 12 80 A 0 80 x 16 12 80 0 80 6 40 B Datum A Datum B 0 2 M A B 119 0 50 0 05 A1 INDEX A B C D E F G H J K L M N P R T 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 0 80 6 40 G BOTTOM VIEW 119 Ball Fine pitch Ball Grid Array Package measured in millimeters PACKAGE DIMENSION MARK ...

Page 646: ...SC32442B RISC MICROPROCESSOR MECHANICAL DATA 1 1 MECHANICAL DATA PACKAGE DIMENSIONS 14 000 14 000 Figure 1 1 332 FBGA SC32442B Package Dimension Top View ...

Page 647: ...MECHANICAL DATA SC32442B RISC MICROPROCESSOR 1 2 0 500 x 25 12 500 0 500 x 25 12 500 0 500 0 500 332 0 300 0 05 Figure 1 2 332 FBGA SC32442B Package Dimension Bottom View ...

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