Ross Synergy 1, Maintenance Manual

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Synergy 1 and Synergy 100 Maintenance Guide (v16-S1) System Architecture • 2–15
27 MHz Clock
Another output from the Deserializer Module is a 27 MHz clock, which is routed to the Phase Lock
Loop ( PLL ). Within the PLL is a stable oscillator that regenerates the 27 MHz clock, filtering out all
jitter and generating the stable (clean) 27 MHz signal that clocks the entire system. The net result is
that if you have a jittery reference signal, the output of the Synergy switcher will not be adversely
affected on its outputs.
If the reference is not present (or is lost), the PLL and SPG still continue to run. In this condition
however, the switcher can default to 625-line mode and the clock rate is not guaranteed. Furthermore,
the switcher may lose lock with the video.
System Timing and Non-Sync Detectors
Non-sync detection is based in the Deserializer Module (4000A-061). As discussed above, a simple
delay can be used, or the module can look at the reference signal and then determine an offset.
The only information that the Deserializer Module has about the reference is Horizontal Sync . The
module itself guarantees that the video will be locked horizontally — after video passes through it.
Additionally, the module’s vertical sync output is examined, and compared to that of the reference. If
the two signals do not match vertically, the system considers the video to be non-synchronous — and
the
N/S (Non-Sync) LED lights on the panel (on the bus on which the source was chosen). In this
non-sync situation, the selected video may be stable, but it will be shifted vertically.
If you have an input signal that is out of the timing window (too far out of time horizontally), the
signal may lock to the next (or to the previous)
Horizontal Sync pulse. This situation, however, can
introduce a one-line offset, either up or down — and the N/S light will again come on.
The Synergy 1 switcher “auto-times” around the reference — on the inputs. Synergy 1 specifications
allow a ¼ line tolerance with regard to timing. If your input is ¼ line early or ¼ line late, relative to
the reference, the system can time it properly and make it lock exactly. If the signal is greater than the
allowed tolerance, the system can not guarantee that it will lock to the correct “H.” It may possibly
lock to the previous H, or to the next H.
Note The PLL loop bandwidth is 300 Hz. Therefore, low frequency jitter
below 300 Hz will not be filtered out by the PLL