14 June, 2002
PCBS
6-47
D
e
tailed
D
escr
iptions
6.4.5 NICF (NETWORK INTERFACE CARD FOR FACSIMILE)
The NICF provides a standard fax IEEE802.3/IEEE802.u LAN interface and uses a
CPU to effect protocol processing.
!
CPU
. An RISC CPU, high performance DSP, and peripheral functions are
combined on one CPU chip (SH7612). The SH7612 receives the requests from
the LANC and option bus and releases the external bus.
"
ASIC (VENUS)
. The ASIC provides the central point for the control of bus
arbitration for CPU access, for option bus and SDRAM access, for SDRAM
refresh, and for management of the internal bus gate.
#
Flash ROM
. The 16 Mbit Flash ROM stores the program code.
$
SDRAM
. The 64 Mbit SDRAM provides shared memory for the option bus and
CPU, the TX/RX buffer for the LAN, the work area for the CPU, and program
area for the CPU.
%
EEPROM
. The EEPROM is a 1 Kbit serial ROM (93C46 compatible). It stores
the MAC addresses and the initial parameters for the LANC register. The MAC
(Medial Access Control) settings are addressed by the wireless LAN to limit
access to the LAN. Immediately after a system reset, the LANC settings are
read out to maintain the settings of the LANC register.
Serial I/F
Connector
CPU
SH7612
Flash
ROM
2 MB
SDRAM
8 MB
EEPROM
1 kB
XTL
25 MHz
XTL
15 MHz
LED
ASIC
VENUS
3 State
Reset SW
LANC
Am79C973
LED
LED
LED
Filter Module
Connector
Connector
Regu
5V
→
3V
!
"
#
$
%
&
'
(
)
LAN I/F
FCU I/F
H310D909.WMF