Renesas M16C Series, User Manual

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R01UH0092EJ0110 Rev.1.10 Page 486 of 807
Jul 31, 2012
M16C/64C Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.2.3 Serial Data Logic Switching Function
The logic of the data written to the UiTB register is inverted and then transmitted. Similarly, the inverted
logic of the received data is read when the UiRB register is read.
Figure 23.15 Serial Data Logic Switching
23.3.2.4 TXD and RXD I/O Polarity Reverse Function
This function reverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all I/O
data (including bits for start, stop, and parity) are inverted.
Figure 23.16 TXD and RXD I/O Polarity Inversion
D0 D1 D2 D3 D4 D5 D6 D7 P SP ST
SP ST D3 D4 D5 D6 D7 P D0 D1 D2
Transmit/
receive clock
TXDi
(not inverted)
TXDi
(inverted)
High
Low
High
Low
High
Low
(1) UiLCH bit in the UiC1 register = 0 (not inverted)
Transmit/
receive clock
High
Low
(2) UiLCH bit in the UiC1 register = 1 (inverted)
i = 0 to 2, 5 to 7
The above assumes the following:
• The CKPOL bit in the UiC0 register is 0 (transmit data output at the falling
edge of the transmit/receive clock).
• The UFORM bit in the UiC0 register is 0 (LSB first).
• The STPS bit in the UiMR register is 0 (1 stop bit).
• The PRYE bit in the UiMR register is 1 (parity enabled).
• The IOPOL bit in the UiMR register is 0 (TXD, RXD I/O not reversed).
ST: Start bit
P: Parity bit
SP: Stop bit
D0 D1 D2 D3 D4 D5 D6 D7 P SP ST
SP ST D3 D4 D5 D6 D7 P D0 D1 D2
Transmit/receive
clock
TXDi
(not inverted)
TXDi
(inverted)
High
Low
High
Low
High
Low
(1) IOPOL bit in the UiMR register = 0 (no reverse)
Transmit/receive
clock
High
Low
(2) IOPOL bit in the UiMR register = 1 (reverse)
D0 D1 D2 D3 D4 D5 D6 D7 P SP ST
RXDi
(not inverted) High
Low
SP ST D3 D4 D5 D6 D7 P D0 D1 D2
RXDi
(inverted)
High
Low
i = 0 to 2, 5 to 7
The above assumes the following:
• The UFORM bit in the UiC0 register is 0 (LSB first).
• The STPS bit in the UiMR register is 0 (1 stop bit).
• The PRYE bit in the UiMR register is 1 (parity enabled).
• The UiLCH bit in the UiC1 register is 0 (serial data logic not inverted).
ST: Start bit
P: Parity bit
SP: Stop bit