R01UH0092EJ0110 Rev.1.10
Page 756 of 807
Jul 31, 2012
M16C/64C Group
31. Electrical Characteristics
V
CC1
= V
CC2
= 3 V
Switching Characteristics
(V
CC1
= V
CC2
= 3 V, V
SS
= 0 V, at T
opr
= -20
°
C to 85
°
C/-40
°
C to 85
°
C unless otherwise specified)
31.3.4.3
In 2 or 3 Waits Setting, and When Accessing External Area and Using
Multiplexed Bus
Notes:
1.
Calculated according to the BCLK frequency as follows:
2.
Calculated according to the BCLK frequency as follows:
n is 2 for 2 waits setting, 3 for 3 waits setting.
3.
Calculated according to the BCLK frequency as follows:
4.
Calculated according to the BCLK frequency as follows:
5.
When using multiplexed bus, set f
(BCLK)
12.5 MHz or less.
6.
Calculated according to the BCLK frequency as follows:
7.
Calculated according to the BCLK frequency as follows:
Table 31.57
Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus)
(5)
Symbol
Parameter
Measuring
Condition
Standard
Unit
Min.
Max.
t
d(BCLK-AD)
Address output delay time
See
50
ns
t
h(BCLK-AD)
Address output hold time (in relation to BCLK)
0
ns
t
h(RD-AD)
Address output hold time (in relation to RD)
ns
t
h(WR-AD)
Address output hold time (in relation to WR)
(Note 6)
ns
t
d(BCLK-CS)
Chip select output delay time
50
ns
t
h(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0
ns
t
h(RD-CS)
Chip select output hold time (in relation to RD)
ns
t
h(WR-CS)
Chip select output hold time (in relation to WR)
ns
t
d(BCLK-RD)
RD signal output delay time
40
ns
t
h(BCLK-RD)
RD signal output hold time
0
ns
t
d(BCLK-WR)
WR signal output delay time
40
ns
t
h(BCLK-WR)
WR signal output hold time
0
ns
t
d(BCLK-DB)
Data output delay time (in relation to BCLK)
50
ns
t
d(DB-WR)
Data output delay time (in relation to WR)
ns
t
h(WR-DB)
Data output hold time (in relation to WR)
(Note 7)
ns
t
d(BCLK-ALE)
ALE signal output delay time (in relation to BCLK)
25
ns
t
h(BCLK-ALE)
ALE signal output hold time (in relation to BCLK)
−
4
ns
t
d(AD-ALE)
ALE signal output delay time (in relation to Address)
ns
t
h(AD-ALE)
ALE signal output hold time (in relation to Address)
ns
t
d(AD-RD)
RD signal output delay from the end of address
0
ns
t
d(AD-WR)
WR signal output delay from the end of address
0
ns
t
dz(RD-AD)
Address output floating start time
8
ns
0.5
10
9
×
f
BCLK
(
)
----------------------
10
ns
[ ]
–
n
0.5
–
(
)
10
9
×
f
BCLK
(
)
------------------------------------
50
ns
[ ]
–
0.5
10
9
×
f
BCLK
(
)
----------------------
40
ns
[ ]
–
0.5
10
9
×
f
BCLK
(
)
----------------------
15
ns
[ ]
–
0.5
10
9
×
f
BCLK
(
)
----------------------
15
ns
[ ]
–
0.5
10
9
×
f
BCLK
(
)
----------------------
25
ns
[ ]
–
Summary of Contents for M16C Series
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