Renesas M16C Series, User Manual

Page: 510 / 846

R01UH0092EJ0110 Rev.1.10 Page 477 of 807
Jul 31, 2012
M16C/64C Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.1.4 Serial Data Logic Switching Function
When the UiLCH bit in the UiC1 register (i = 0 to 2, 5 to 7) is 1 (inverted), the data written to the UiTB
register has its logic inverted before being transmitted. Similarly, the inverted data has its logic inverted
when read from the UiRB register. Figure 23.9 shows Serial Data Logic.
Figure 23.9 Serial Data Logic
23.3.1.5 Transmit/Receive Clock Output from Multiple Pins (UART1)
Use bits CLKMD1 to CLKMD0 in the UCON register to select one of the two transmit/receive clock
output pins (see Figure 23.10). This function can be used when the selected transmit/receive clock
for UART1 is an internal clock.
Figure 23.10 Transmit/Receive Clock Output from Multiple Pins
D0 D1 D2 D3 D4 D5 D6 D7
Transmit/receive clock
TXDi
(not inverted)
(1) UiLCH bit in the UiC1 register is 0 (not inverted)
(2) UiLCH bit in the UiC1 register is 1 (inverted)
Low
High
Low
D0 D1 D2 D3 D4 D5 D6 D7
Transmit/receive clock
TXDi
(inverted)
High
Low
High
Low
High
i = 0 to 2, 5 to 7
The above assumes the following:
• The CKPOL bit in the UiC0 register is 0 (transmit data output at the falling edge of the
transmit/receive clock).
• The UFORM bit in the UiC0 register is 0 (LSB first).
MCU
TXD1 (P6_7)
CLKS1 (P6_4)
CLK1 (P6_5) IN
CLK
IN
CLK
Transmit/receive enabled when the
CLKMD0 bit in the UCON register is 0 Transmit/receive enabled when the
CLKMD0 bit in the UCON register is 1
The above diagram assumes the following:
y
The CKDIR bit in the U1MR register is 0 (internal clock).
y
The CLKMD1 bit in the UCON register is 1 (transmit/receive clock output from multiple pins).