R01UH0092EJ0110 Rev.1.10
Page 93 of 807
Jul 31, 2012
M16C/64C Group
8. Clock Generator
8.2.5
Peripheral Clock Select Register (PCLKR)
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.
PCLK5 (Clock output function extension bit) (b5)
The PCLK5 bit is enabled in single-chip mode. Output from the CLKOUT pin is selectable. When the
PCLK5 bit is 1, set bits CM01 and CM00 to 00b. See Table 8.4 “CLKOUT Pin Functions in Single-Chip
Mode”.
8.2.6
Peripheral Clock Stop Register 1 (PCLKSTP1)
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.
Peripheral Clock Select Register
b7
0
0
0
0
0
b6 b5 b4
b1
b2
b3
Symbol
PCLKR
Address
0012h
Bit Symbol
Bit Name
RW
Reset Value
0000 0011b
b0
Function
—
(b4-b2)
RW
Reserved bits
Set to 0
—
(b7-b6)
RW
Reserved bits
Set to 0
PCLK5
RW
Clock output function
expansion bit
(enabled in single-chip mode)
0: Selected by setting bits CM01 to CM00
in the CM0 register
1: Output f1
PCLK0
Timers A and B clock select bit
(clock source for timers A and
B, the dead time timer, and
multi-master I
2
C-bus interface)
0: f2TIMAB/f2IIC
1: f1TIMAB/f1IIC
RW
PCLK1
RW
SI/O clock select bit
(clock source for UART0 to
UART2, UART5 to UART7,
SI/O3, and SI/O4)
0: f2SIO
1: f1SIO
b7 b6 b5 b4 b3 b2 b1 b0
Peripheral Clock Stop Register 1
Symbol
PCLKSTP1
Address
0016h
Reset Value
0XXX XX00b
Bit Symbol
Bit Name
Function
RW
PCKSTP17
Timer clock source select bit
(timer A, timer B)
—
(b6-b2)
No register bit. If necessary, set to 0. The read value is undefined.
—
Peripheral clock stop bit
(other than timer A, timer B)
PCKSTP1A
PCKSTP11
Timer peripheral clock stop bit
(timer A, timer B)
0: f1 provide enabled
1: f1 provide disabled
0: f1 provide enabled
1: f1 provide disabled
0: f1
1: Main clock
RW
RW
RW
Summary of Contents for M16C Series
Page 846: ...M16C 64C Group R01UH0092EJ0110...
