Renesas M16C Series, User Manual

Page: 263 / 846

R01UH0092EJ0110 Rev.1.10 Page 230 of 807
Jul 31, 2012
M16C/64C Group 15. Watchdog Timer
15.4 Operations
15.4.1 Count Source Protection Mode Disabled
The CPU clock is used as the watchdog timer count source when count source protection mode is
disabled.
Table 15.3 lists Watchdog Timer Specifications (Count Source Protection Mode Disabled).
Table 15.3 Watchdog Timer Specifications (Count Source Protection Mode Disabled)
Item Specification
Count source CPU clock
Count operation Decrement
Cycles
When the CM07 bit in the CM0 register is 0 (main clock, PLL clock, fOCO-S):
n: 16 or 128 (selected by the WDC7 bit in the WDC register)
Example: When CPU clock frequency is 16 MHz and the prescaler division rate is
16, the watchdog timer cycle is approximately 32.8 ms.
When the CM07 bit is 1 (sub clock):
Watchdog timer
counter refresh
timing
•
Reset (refer to 6. “Resets”)
•
Write 00h, and then FFh to the WDTR register.
•
Underflow
Count start
conditions
Set the WDTON bit in the OFS1 address to select the watchdog timer operation
after reset.
•
WDTON bit is 1 (watchdog timer is in stop state after reset)
The watchdog timer counter and prescaler stop after reset and count starts by
writing to the WDTS register.
•
WDTON bit is 0 (watchdog timer starts automatically after reset)
The watchdog timer counter and prescaler start counting automatically after reset.
Count stop
conditions
•
Stop mode
•
Wait mode
•
Bus hold
(Count resumes from the hold value after exiting.)
Operation when
timer underflows
•
PM12 bit in the PM1 register is 0
Watchdog timer interrupt
•
PM12 bit in the PM1 register is 1
Watchdog timer reset (Refer to 6.4.8 “Watchdog Timer Reset”.)
Note:
1. When writing 00h and then FFh to the WDTR register, the watchdog timer is refreshed, but the
prescaler is not initialized. Thus, some errors in the watchdog timer period may be caused by the
prescaler. The prescaler is initialized after reset.
Prescaler divide value (n) watchdog timer count value (32768)
×
CPU clock
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
(1)
Prescaler divide value (2) watchdog timer count value (32768)
×
CPU clock
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
(1)