Renesas M16C Series, User Manual

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R01UH0092EJ0110 Rev.1.10 Page 518 of 807
Jul 31, 2012
M16C/64C Group 23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.5.3.3 Low/High-level Input Voltage and Low-level Output Voltage
The low-level input voltage, high-level input voltage, and low-level output voltage differ from the I
2
C-
bus specification.
Refer to the recommended operating conditions for I/O ports which share the pins with SCL and
SDA.
I
2
C-bus specification
High level input voltage (V
IH
) = min. 0.7 V
CC
Low level input voltage (V
IL
) = max. 0.3 V
CC
23.5.3.4 Setup and Hold Times When Generating a Start/Stop Condition
When generating a start condition, the hold time (t
HD
:STA) is a half cycle of the SCL clock. When
generating a stop condition, the setup time (t
SU
:STO) is a half cycle of the SCL clock.
When the SDA digital delay function is enabled, take delay time into consideration (see 23.3.3.7
“SDA Digital Delay”).
The following shows a calculation example of hold and setup times when generating a start/stop
condition.
Calculation example when setting 100 kbps
•
UiBRG count source: f1 = 20 MHz
•
UiBRG register setting value: n = 100 - 1
•
SDA digital delay setting value: DL2 to DL0 are 101b (5 or 6 cycles of UiBRG count source)
f
SCL
(theoretical value) = f1 / (2(n+1)) = 20 MHz / (2
×
(99 + 1)) = 100 kbps
t
DL
= delay cycle count / f1 = 6 / 20 MHz = 0.3
μ
s
t
HD:STA
(theoretical value) = 1 / (2f
SCL
(theoretical value)) = 1 / (2
×
100 kbps) = 5
μ
s
t
SU:STO
(theoretical value) = 1 / (2f
SCL
(theoretical value)) = 1 / (2
×
100 kbps) = 5
μ
s
f
HD:STA
(actual value) = t
HD:STA
(theoretical value) - t
DL
= 5
μ
s - 0.3
μ
s = 4.7
μ
s
f
SU:STO
(actual value) = t
SU:STO
(theoretical value) + t
DL
= 5
μ
s + 0.3
μ
s = 5.3
μ
s
Figure 23.39 Setup and Hold Times When Generating Start and Stop Conditions
t
DL
SCL
SDA
f
SCL
: SCL clock
t
DL
: SDA digital delay time
t
HD:STA
: Hold time when generating a start condition
t
SU:STO
: Set-up time when generating a stop condition
t
SU:STO
(theoretical value)
t
SU:STO
(actual value)
t
DL
1 / f
SCL
(theoretical value)
1 / (2f
SCL
(theoretical value))
t
HD:STA
(actual value)
t
HD:STA
(theoretical value)
1 / (2f
SCL
(theoretical value))
Internal clock
(UiBRG output)