Renesas M16C Series, User Manual

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C - 2
2. Items revised or added in previous versions
REVISION HISTORY M16C/64C Group User’s Manual: Hardware
Rev. Date
Description
Page Summary
0.10 Oct 29, 2010 - First Edition issued.
1.00 Feb 07, 2011
Overall
Changed terminologies are as follows:
• “oscillation/oscillator circuit” to “oscillator”
• “oscillator” to “a crystal/ceramic resonator”
• “oscillator manufacturer” to “manufacturer of crystal/ceramic resonator”
• “on-chip oscillator oscillation circuit” to “on-chip oscillator”
Overview
3
Table 1.2 Specifications for the 100-Pin Package (2/2): Changed the Description column of the
Current Consumption row.
4
Table 1.3 Product List (N-Version), Table 1.4 Product List (D-Version): Changed the development
status.
Clock Generator
92
8.2.6 Peripheral Clock Stop Register 1 (PCLKSTP1): Deleted the description of fOCO-F and
fOCO40M.
97
8.3.2 PLL Clock: Modified the explanation of how to generate PLL clock from the main clock.
Power Control
128
9.6.3 Stop Mode: Changed “before the WAIT instruction is executed” to “before entering stop
mode” in the last sentence of the third bullet.
Interrupt
216
14.10 Key Input Interrupt: Modified the explanation of the condition for the IR bit in the KUPIC
register to become 1.
Timer A
256
17.2.3 Peripheral Clock Stop Register 1 (PCLKSTP1): Deleted the description of fOCO-F and
fOCO40M.
Timer B
305
18.2.3 Peripheral Clock Stop Register 1 (PCLKSTP1): Deleted the description of fOCO-F and
fOCO40M.
306, 307
18.2.4 Timer Bi Register (TBi) (i = 0 to 5), 18.2.5 Timer Bi-1 Register (TBi1) (i = 0 to 5):
Modified the Reset Value.
Serial Interface UARTi
481
Figure 23.13 Receive Timing in UART Mode:
Modified “UiBRG count source” to “Clock divided by UiBRG”.
Multi-Master I
2
C-bus Interface
569
Figure 25.15 Operation When Transmitted/Received a Slave Address or Data: Changed the
description of bits TRX, ADR0, and AAS in parenthesis for when a slave address is received.
Flash Memory
674
Table 30.12 Modes after Executing Commands (in EW0 Mode): Changed the Mode after Executing
Command of the Clear status register.
Electrical Characteristics
VCC = 5 V
722, 723
Table 31.19 Electrical Characteristics (3), Table 31.20 Electrical Characteristics (4):
Added conditions when XIN is 6MHz to the Wait mode measuring condition.
732, 735,
737
In Switching Characteristics (Memory Expansion Mode and Microprocessor Mode),
Table 31.35, Table 31.36, Table 31.37:
• Deleted the th(BCLK-DB) row.
• Changed the formula of th(WR-DB) for minimum standard.
734, 736,
738
Figure 31.15, Figure 31.16, Figure 31.17:
Deleted the description of th(BCLK-DB), and changed the formula of th(WR-DB) in the Write
timing.
VCC = 3 V
740, 741
Table 31.39 Electrical Characteristics (2), Table 31.40 Electrical Characteristics (3):
Added conditions when XIN is 6MHz to the Wait mode measuring condition.