Renesas M16C Series, User Manual

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R01UH0092EJ0110 Rev.1.10 Page 140 of 807
Jul 31, 2012
M16C/64C Group 11. Bus
11.2.2 Chip Select Expansion Control Register (CSE)
Set the CSiW bit (i = 0 to 3) in the CSR register to 0 (wait state) before writing to bits CSEi1W to
CSEi0W. To set the CSiW bit to 1 (no wait state), set bits CSEi1W to CSEi0W to 00b first, and then set
the CSiW bit to 1.
b7 b6 b5 b4 b1 b2 b3
Chip Select Expansion Control Register
Symbol
CSE
Address
001Bh
Bit Symbol Bit Name
RW
Reset Value
00h
b0
Function
b1 b0
0 0 : 1 wait (1
φ
+ 1
φ
)
0 1 : 2 waits (1
φ
+ 2
φ
)
1 0 : 3 waits (1
φ
+ 3
φ
)
1 1 : Do not set.
CS0 wait expansion bit
b3 b2
0 0 : 1 wait (1
φ
+ 1
φ
)
0 1 : 2 waits (1
φ
+ 2
φ
)
1 0 : 3 waits (1
φ
+ 3
φ
)
1 1 : Do not set.
CS1 wait expansion bit
b5 b4
0 0 : 1 wait (1
φ
+ 1
φ
)
0 1 : 2 waits (1
φ
+ 2
φ
)
1 0 : 3 waits (1
φ
+ 3
φ
)
1 1 : Do not set.
CS2 wait expansion bit
b7 b6
0 0 : 1 wait (1
φ
+ 1
φ
)
0 1 : 2 waits (1
φ
+ 2
φ
)
1 0 : 3 waits (1
φ
+ 3
φ
)
1 1 : Do not set.
CS3 wait expansion bit
CSE00W RW
CSE01W RW
CSE10W RW
CSE11W RW
CSE20W RW
CSE21W RW
CSE30W RW
CSE31W RW