R01UH0092EJ0110 Rev.1.10
Page 770 of 807
Jul 31, 2012
M16C/64C Group
32. Usage Notes
32.7
Notes on Bus
32.7.1
Reading Data Flash
When 2.7 V
≤
VCC1
≤
3.0 V and f(BCLK)
≥
16 MHz, or when 3.0 V < VCC1
≤
5.5 V and f(BCLK)
≥
20
MHz, one wait must be inserted to read the data flash. Use the PM17 bit or the FMR17 bit to insert one
wait.
32.7.2
External Bus
When a hardware reset, power-on reset, or voltage monitor 0 reset is performed with a high-level input
on the CNVSS pin, the internal ROM cannot be read.
32.7.3
External Access Immediately after Writing to the SFRs
When accessing an external device after writing to the SFRs, the write signal and
CSi
signal switch
simultaneously. Thus, adjust the capacity of each signal so as not to delay the write signal.
32.7.4
HOLD
HOLD
input is unavailable. Connect the
HOLD
pin to VCC2 via a resistor (pull-up).
Summary of Contents for M16C Series
Page 846: ...M16C 64C Group R01UH0092EJ0110...
