Renesas M16C/62P Group, Hardware Manual

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M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface
Rev.2.41 Jan 10, 2006 Page 200 of 390
REJ09B0185-0241
Figure 17.19 Transmit Operation
D0 D1 D2 D3 D4 D5 D6 D7 ST P
Parity
bit
TXDi
CTSi
“0”
“1”
“0”
“1”
“H”
“0”
“1”
“0”
“1”
Set to “0” by an interrupt request acknowledgement or by program
D0 D1 D2 D3 D4 D5 D6 D7 ST P
D0 D1 ST
TXDi
“0”
“1”
“0”
“1”
“0”
“1”
Transfer Clock
Tc
“0”
“1”
Set to “0” by an interrupt request acknowledgement or by program
Tc
Transfer Clock
Stop
bit
Data is set in the UiTB register
Data is transferred from the UiTB register to
the UARTi transmit register
D0
D1 D2
D3
D4 D5 D6
D7 ST D8 D0
D1 D2
D3
D4 D5 D6
D7 ST
D8
D0
D1
ST
SP SP
The transfer clock stops momentarily, because an “H” single is applied to the CTS pin,
when the stop bit is verified.
The transfer clock resumes running as soon as an “L” single is applied to the CTS pin.
Data is set in the UiTB register
SP
Data is transferred from the UiTB register to the UARTi transmit register
TE bit in UiC1
register
TI bit in UiC1
register
TXEPT bit in UiC0
register
IR bit in
SiTIC register
TE bit in UiC1
register
TI bit in UiC1
register
TXEPT bit in
UiC0 register
IR bit in
SiTIC register
i=0 to 2
“L”
Pulse stops because the TE bit is set to “0”
SP SP
Start bit
SP
(1) 8-bit Data Transmit Timing (with a parity and 1 stop bit)
(1) 9-bit Data Transmit Timing (with no parity and 2 stop bits)
Stop
bit
Start bit
Stop
bit
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
The above timing diagram applies to the case where the register bits are set
as follows:
· PRYE bit in UiMR register = 1 (parity enabled)
· STPS bit in UiMR register = 0 (1 stop bit)
· CRD bit in UiC0 register = 0 (CTS/RTS enabled) and
CRS bit = 0 (CTS selected)
· UiIRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
i=0 to 2
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
The above timing diagram applies to the case where the register bits are set
as follows:
· PRYE bit in UiMR register = 0 (parity disabled)
· STPS bit in UiMR register = 1 (2 stop bits)
· CRD bit in UiC0 register = 1 (CTS/RTS disabled)
· UiIRS bit = 0 (an interrupt request occurs when transmit
buffer becomes empty):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
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